/*
 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/*
 * //depot/chips/scorpion/1.0/rtl/apb/blueprint/apb_map.h
 * /trees/paddu/paddu-scorpion/chips/scorpion/1.0/rtl/apb/blueprint/apb_map.h
 */

#ifndef	_944x_H
#define	_944x_H

// 0x18000000	DDR_CONFIG
#define DDR_CONFIG_CAS_LATENCY_MSB_MSB				31
#define DDR_CONFIG_CAS_LATENCY_MSB_LSB				31
#define DDR_CONFIG_CAS_LATENCY_MSB_MASK				0x80000000
#define DDR_CONFIG_CAS_LATENCY_MSB_GET(x)			(((x) & DDR_CONFIG_CAS_LATENCY_MSB_MASK) >> DDR_CONFIG_CAS_LATENCY_MSB_LSB)
#define DDR_CONFIG_CAS_LATENCY_MSB_SET(x)			(((x) << DDR_CONFIG_CAS_LATENCY_MSB_LSB) & DDR_CONFIG_CAS_LATENCY_MSB_MASK)
#define DDR_CONFIG_CAS_LATENCY_MSB_RESET			0x0 // 0
#define DDR_CONFIG_OPEN_PAGE_MSB				30
#define DDR_CONFIG_OPEN_PAGE_LSB				30
#define DDR_CONFIG_OPEN_PAGE_MASK				0x40000000
#define DDR_CONFIG_OPEN_PAGE_GET(x)				(((x) & DDR_CONFIG_OPEN_PAGE_MASK) >> DDR_CONFIG_OPEN_PAGE_LSB)
#define DDR_CONFIG_OPEN_PAGE_SET(x)				(((x) << DDR_CONFIG_OPEN_PAGE_LSB) & DDR_CONFIG_OPEN_PAGE_MASK)
#define DDR_CONFIG_OPEN_PAGE_RESET				0x1 // 1
#define DDR_CONFIG_CAS_LATENCY_MSB				29
#define DDR_CONFIG_CAS_LATENCY_LSB				27
#define DDR_CONFIG_CAS_LATENCY_MASK				0x38000000
#define DDR_CONFIG_CAS_LATENCY_GET(x)				(((x) & DDR_CONFIG_CAS_LATENCY_MASK) >> DDR_CONFIG_CAS_LATENCY_LSB)
#define DDR_CONFIG_CAS_LATENCY_SET(x)				(((x) << DDR_CONFIG_CAS_LATENCY_LSB) & DDR_CONFIG_CAS_LATENCY_MASK)
#define DDR_CONFIG_CAS_LATENCY_RESET				0x6 // 6
#define DDR_CONFIG_TMRD_MSB					26
#define DDR_CONFIG_TMRD_LSB					23
#define DDR_CONFIG_TMRD_MASK					0x07800000
#define DDR_CONFIG_TMRD_GET(x)					(((x) & DDR_CONFIG_TMRD_MASK) >> DDR_CONFIG_TMRD_LSB)
#define DDR_CONFIG_TMRD_SET(x)					(((x) << DDR_CONFIG_TMRD_LSB) & DDR_CONFIG_TMRD_MASK)
#define DDR_CONFIG_TMRD_RESET					0xf // 15
#define DDR_CONFIG_TRFC_MSB					22
#define DDR_CONFIG_TRFC_LSB					17
#define DDR_CONFIG_TRFC_MASK					0x007e0000
#define DDR_CONFIG_TRFC_GET(x)					(((x) & DDR_CONFIG_TRFC_MASK) >> DDR_CONFIG_TRFC_LSB)
#define DDR_CONFIG_TRFC_SET(x)					(((x) << DDR_CONFIG_TRFC_LSB) & DDR_CONFIG_TRFC_MASK)
#define DDR_CONFIG_TRRD_MSB					16
#define DDR_CONFIG_TRRD_LSB					13
#define DDR_CONFIG_TRRD_MASK					0x0001e000
#define DDR_CONFIG_TRRD_GET(x)					(((x) & DDR_CONFIG_TRRD_MASK) >> DDR_CONFIG_TRRD_LSB)
#define DDR_CONFIG_TRRD_SET(x)					(((x) << DDR_CONFIG_TRRD_LSB) & DDR_CONFIG_TRRD_MASK)
#define DDR_CONFIG_TRRD_RESET					0x4 // 4
#define DDR_CONFIG_TRP_MSB					12
#define DDR_CONFIG_TRP_LSB					9
#define DDR_CONFIG_TRP_MASK					0x00001e00
#define DDR_CONFIG_TRP_GET(x)					(((x) & DDR_CONFIG_TRP_MASK) >> DDR_CONFIG_TRP_LSB)
#define DDR_CONFIG_TRP_SET(x)					(((x) << DDR_CONFIG_TRP_LSB) & DDR_CONFIG_TRP_MASK)
#define DDR_CONFIG_TRP_RESET					0x6 // 6
#define DDR_CONFIG_TRCD_MSB					8
#define DDR_CONFIG_TRCD_LSB					5
#define DDR_CONFIG_TRCD_MASK					0x000001e0
#define DDR_CONFIG_TRCD_GET(x)					(((x) & DDR_CONFIG_TRCD_MASK) >> DDR_CONFIG_TRCD_LSB)
#define DDR_CONFIG_TRCD_SET(x)					(((x) << DDR_CONFIG_TRCD_LSB) & DDR_CONFIG_TRCD_MASK)
#define DDR_CONFIG_TRCD_RESET					0x6 // 6
#define DDR_CONFIG_TRAS_MSB					4
#define DDR_CONFIG_TRAS_LSB					0
#define DDR_CONFIG_TRAS_MASK					0x0000001f
#define DDR_CONFIG_TRAS_GET(x)					(((x) & DDR_CONFIG_TRAS_MASK) >> DDR_CONFIG_TRAS_LSB)
#define DDR_CONFIG_TRAS_SET(x)					(((x) << DDR_CONFIG_TRAS_LSB) & DDR_CONFIG_TRAS_MASK)
#define DDR_CONFIG_ADDRESS					0x18000000

// 0x18000004	DDR_CONFIG2
#define DDR_CONFIG2_HALF_WIDTH_LOW_MSB				31
#define DDR_CONFIG2_HALF_WIDTH_LOW_LSB				31
#define DDR_CONFIG2_HALF_WIDTH_LOW_MASK				0x80000000
#define DDR_CONFIG2_HALF_WIDTH_LOW_GET(x)			(((x) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK) >> DDR_CONFIG2_HALF_WIDTH_LOW_LSB)
#define DDR_CONFIG2_HALF_WIDTH_LOW_SET(x)			(((x) << DDR_CONFIG2_HALF_WIDTH_LOW_LSB) & DDR_CONFIG2_HALF_WIDTH_LOW_MASK)
#define DDR_CONFIG2_HALF_WIDTH_LOW_RESET			0x1 // 1
#define DDR_CONFIG2_SWAP_A26_A27_MSB				30
#define DDR_CONFIG2_SWAP_A26_A27_LSB				30
#define DDR_CONFIG2_SWAP_A26_A27_MASK				0x40000000
#define DDR_CONFIG2_SWAP_A26_A27_GET(x)				(((x) & DDR_CONFIG2_SWAP_A26_A27_MASK) >> DDR_CONFIG2_SWAP_A26_A27_LSB)
#define DDR_CONFIG2_SWAP_A26_A27_SET(x)				(((x) << DDR_CONFIG2_SWAP_A26_A27_LSB) & DDR_CONFIG2_SWAP_A26_A27_MASK)
#define DDR_CONFIG2_SWAP_A26_A27_RESET				0x0 // 0
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MSB			29
#define DDR_CONFIG2_GATE_OPEN_LATENCY_LSB			26
#define DDR_CONFIG2_GATE_OPEN_LATENCY_MASK			0x3c000000
#define DDR_CONFIG2_GATE_OPEN_LATENCY_GET(x)			(((x) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK) >> DDR_CONFIG2_GATE_OPEN_LATENCY_LSB)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_SET(x)			(((x) << DDR_CONFIG2_GATE_OPEN_LATENCY_LSB) & DDR_CONFIG2_GATE_OPEN_LATENCY_MASK)
#define DDR_CONFIG2_GATE_OPEN_LATENCY_RESET			0x6 // 6
#define DDR_CONFIG2_TWTR_MSB					25
#define DDR_CONFIG2_TWTR_LSB					21
#define DDR_CONFIG2_TWTR_MASK					0x03e00000
#define DDR_CONFIG2_TWTR_GET(x)					(((x) & DDR_CONFIG2_TWTR_MASK) >> DDR_CONFIG2_TWTR_LSB)
#define DDR_CONFIG2_TWTR_SET(x)					(((x) << DDR_CONFIG2_TWTR_LSB) & DDR_CONFIG2_TWTR_MASK)
#define DDR_CONFIG2_TWTR_RESET					0xe // 14
#define DDR_CONFIG2_TRTP_MSB					20
#define DDR_CONFIG2_TRTP_LSB					17
#define DDR_CONFIG2_TRTP_MASK					0x001e0000
#define DDR_CONFIG2_TRTP_GET(x)					(((x) & DDR_CONFIG2_TRTP_MASK) >> DDR_CONFIG2_TRTP_LSB)
#define DDR_CONFIG2_TRTP_SET(x)					(((x) << DDR_CONFIG2_TRTP_LSB) & DDR_CONFIG2_TRTP_MASK)
#define DDR_CONFIG2_TRTP_RESET					0x8 // 8
#define DDR_CONFIG2_TRTW_MSB					16
#define DDR_CONFIG2_TRTW_LSB					12
#define DDR_CONFIG2_TRTW_MASK					0x0001f000
#define DDR_CONFIG2_TRTW_GET(x)					(((x) & DDR_CONFIG2_TRTW_MASK) >> DDR_CONFIG2_TRTW_LSB)
#define DDR_CONFIG2_TRTW_SET(x)					(((x) << DDR_CONFIG2_TRTW_LSB) & DDR_CONFIG2_TRTW_MASK)
#define DDR_CONFIG2_TWR_MSB					11
#define DDR_CONFIG2_TWR_LSB					8
#define DDR_CONFIG2_TWR_MASK					0x00000f00
#define DDR_CONFIG2_TWR_GET(x)					(((x) & DDR_CONFIG2_TWR_MASK) >> DDR_CONFIG2_TWR_LSB)
#define DDR_CONFIG2_TWR_SET(x)					(((x) << DDR_CONFIG2_TWR_LSB) & DDR_CONFIG2_TWR_MASK)
#define DDR_CONFIG2_TWR_RESET					0x6 // 6
#define DDR_CONFIG2_CKE_MSB					7
#define DDR_CONFIG2_CKE_LSB					7
#define DDR_CONFIG2_CKE_MASK					0x00000080
#define DDR_CONFIG2_CKE_GET(x)					(((x) & DDR_CONFIG2_CKE_MASK) >> DDR_CONFIG2_CKE_LSB)
#define DDR_CONFIG2_CKE_SET(x)					(((x) << DDR_CONFIG2_CKE_LSB) & DDR_CONFIG2_CKE_MASK)
#define DDR_CONFIG2_CKE_RESET					0x0 // 0
#define DDR_CONFIG2_PHASE_SELECT_MSB				6
#define DDR_CONFIG2_PHASE_SELECT_LSB				6
#define DDR_CONFIG2_PHASE_SELECT_MASK				0x00000040
#define DDR_CONFIG2_PHASE_SELECT_GET(x)				(((x) & DDR_CONFIG2_PHASE_SELECT_MASK) >> DDR_CONFIG2_PHASE_SELECT_LSB)
#define DDR_CONFIG2_PHASE_SELECT_SET(x)				(((x) << DDR_CONFIG2_PHASE_SELECT_LSB) & DDR_CONFIG2_PHASE_SELECT_MASK)
#define DDR_CONFIG2_PHASE_SELECT_RESET				0x0 // 0
#define DDR_CONFIG2_CNTL_OE_EN_MSB				5
#define DDR_CONFIG2_CNTL_OE_EN_LSB				5
#define DDR_CONFIG2_CNTL_OE_EN_MASK				0x00000020
#define DDR_CONFIG2_CNTL_OE_EN_GET(x)				(((x) & DDR_CONFIG2_CNTL_OE_EN_MASK) >> DDR_CONFIG2_CNTL_OE_EN_LSB)
#define DDR_CONFIG2_CNTL_OE_EN_SET(x)				(((x) << DDR_CONFIG2_CNTL_OE_EN_LSB) & DDR_CONFIG2_CNTL_OE_EN_MASK)
#define DDR_CONFIG2_CNTL_OE_EN_RESET				0x1 // 1
#define DDR_CONFIG2_BURST_TYPE_MSB				4
#define DDR_CONFIG2_BURST_TYPE_LSB				4
#define DDR_CONFIG2_BURST_TYPE_MASK				0x00000010
#define DDR_CONFIG2_BURST_TYPE_GET(x)				(((x) & DDR_CONFIG2_BURST_TYPE_MASK) >> DDR_CONFIG2_BURST_TYPE_LSB)
#define DDR_CONFIG2_BURST_TYPE_SET(x)				(((x) << DDR_CONFIG2_BURST_TYPE_LSB) & DDR_CONFIG2_BURST_TYPE_MASK)
#define DDR_CONFIG2_BURST_TYPE_RESET				0x0 // 0
#define DDR_CONFIG2_BURST_LENGTH_MSB				3
#define DDR_CONFIG2_BURST_LENGTH_LSB				0
#define DDR_CONFIG2_BURST_LENGTH_MASK				0x0000000f
#define DDR_CONFIG2_BURST_LENGTH_GET(x)				(((x) & DDR_CONFIG2_BURST_LENGTH_MASK) >> DDR_CONFIG2_BURST_LENGTH_LSB)
#define DDR_CONFIG2_BURST_LENGTH_SET(x)				(((x) << DDR_CONFIG2_BURST_LENGTH_LSB) & DDR_CONFIG2_BURST_LENGTH_MASK)
#define DDR_CONFIG2_BURST_LENGTH_RESET				0x8 // 8
#define DDR_CONFIG2_ADDRESS					0x18000004

// 0x18000008	DDR_MODE_REGISTER
#define DDR_MODE_REGISTER_VALUE_MSB				13
#define DDR_MODE_REGISTER_VALUE_LSB				0
#define DDR_MODE_REGISTER_VALUE_MASK				0x00003fff
#define DDR_MODE_REGISTER_VALUE_GET(x)				(((x) & DDR_MODE_REGISTER_VALUE_MASK) >> DDR_MODE_REGISTER_VALUE_LSB)
#define DDR_MODE_REGISTER_VALUE_SET(x)				(((x) << DDR_MODE_REGISTER_VALUE_LSB) & DDR_MODE_REGISTER_VALUE_MASK)
#define DDR_MODE_REGISTER_ADDRESS				0x18000008

// 0x1800000c	DDR_EXTENDED_MODE_REGISTER
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MSB			13
#define DDR_EXTENDED_MODE_REGISTER_VALUE_LSB			0
#define DDR_EXTENDED_MODE_REGISTER_VALUE_MASK			0x00003fff
#define DDR_EXTENDED_MODE_REGISTER_VALUE_GET(x)			(((x) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK) >> DDR_EXTENDED_MODE_REGISTER_VALUE_LSB)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_SET(x)			(((x) << DDR_EXTENDED_MODE_REGISTER_VALUE_LSB) & DDR_EXTENDED_MODE_REGISTER_VALUE_MASK)
#define DDR_EXTENDED_MODE_REGISTER_VALUE_RESET			0x2 // 2
#define DDR_EXTENDED_MODE_REGISTER_ADDRESS			0x1800000c

// 0x18000010	DDR_CONTROL
#define DDR_CONTROL_EMR3S_MSB					5
#define DDR_CONTROL_EMR3S_LSB					5
#define DDR_CONTROL_EMR3S_MASK					0x00000020
#define DDR_CONTROL_EMR3S_GET(x)				(((x) & DDR_CONTROL_EMR3S_MASK) >> DDR_CONTROL_EMR3S_LSB)
#define DDR_CONTROL_EMR3S_SET(x)				(((x) << DDR_CONTROL_EMR3S_LSB) & DDR_CONTROL_EMR3S_MASK)
#define DDR_CONTROL_EMR3S_RESET					0x0 // 0
#define DDR_CONTROL_EMR2S_MSB					4
#define DDR_CONTROL_EMR2S_LSB					4
#define DDR_CONTROL_EMR2S_MASK					0x00000010
#define DDR_CONTROL_EMR2S_GET(x)				(((x) & DDR_CONTROL_EMR2S_MASK) >> DDR_CONTROL_EMR2S_LSB)
#define DDR_CONTROL_EMR2S_SET(x)				(((x) << DDR_CONTROL_EMR2S_LSB) & DDR_CONTROL_EMR2S_MASK)
#define DDR_CONTROL_EMR2S_RESET					0x0 // 0
#define DDR_CONTROL_PREA_MSB					3
#define DDR_CONTROL_PREA_LSB					3
#define DDR_CONTROL_PREA_MASK					0x00000008
#define DDR_CONTROL_PREA_GET(x)					(((x) & DDR_CONTROL_PREA_MASK) >> DDR_CONTROL_PREA_LSB)
#define DDR_CONTROL_PREA_SET(x)					(((x) << DDR_CONTROL_PREA_LSB) & DDR_CONTROL_PREA_MASK)
#define DDR_CONTROL_PREA_RESET					0x0 // 0
#define DDR_CONTROL_REF_MSB					2
#define DDR_CONTROL_REF_LSB					2
#define DDR_CONTROL_REF_MASK					0x00000004
#define DDR_CONTROL_REF_GET(x)					(((x) & DDR_CONTROL_REF_MASK) >> DDR_CONTROL_REF_LSB)
#define DDR_CONTROL_REF_SET(x)					(((x) << DDR_CONTROL_REF_LSB) & DDR_CONTROL_REF_MASK)
#define DDR_CONTROL_REF_RESET					0x0 // 0
#define DDR_CONTROL_EMRS_MSB					1
#define DDR_CONTROL_EMRS_LSB					1
#define DDR_CONTROL_EMRS_MASK					0x00000002
#define DDR_CONTROL_EMRS_GET(x)					(((x) & DDR_CONTROL_EMRS_MASK) >> DDR_CONTROL_EMRS_LSB)
#define DDR_CONTROL_EMRS_SET(x)					(((x) << DDR_CONTROL_EMRS_LSB) & DDR_CONTROL_EMRS_MASK)
#define DDR_CONTROL_EMRS_RESET					0x0 // 0
#define DDR_CONTROL_MRS_MSB					0
#define DDR_CONTROL_MRS_LSB					0
#define DDR_CONTROL_MRS_MASK					0x00000001
#define DDR_CONTROL_MRS_GET(x)					(((x) & DDR_CONTROL_MRS_MASK) >> DDR_CONTROL_MRS_LSB)
#define DDR_CONTROL_MRS_SET(x)					(((x) << DDR_CONTROL_MRS_LSB) & DDR_CONTROL_MRS_MASK)
#define DDR_CONTROL_MRS_RESET					0x0 // 0
#define DDR_CONTROL_ADDRESS					0x18000010

// 0x18000014	DDR_REFRESH
#define DDR_REFRESH_ENABLE_MSB					14
#define DDR_REFRESH_ENABLE_LSB					14
#define DDR_REFRESH_ENABLE_MASK					0x00004000
#define DDR_REFRESH_ENABLE_GET(x)				(((x) & DDR_REFRESH_ENABLE_MASK) >> DDR_REFRESH_ENABLE_LSB)
#define DDR_REFRESH_ENABLE_SET(x)				(((x) << DDR_REFRESH_ENABLE_LSB) & DDR_REFRESH_ENABLE_MASK)
#define DDR_REFRESH_ENABLE_RESET				0x0 // 0
#define DDR_REFRESH_PERIOD_MSB					13
#define DDR_REFRESH_PERIOD_LSB					0
#define DDR_REFRESH_PERIOD_MASK					0x00003fff
#define DDR_REFRESH_PERIOD_GET(x)				(((x) & DDR_REFRESH_PERIOD_MASK) >> DDR_REFRESH_PERIOD_LSB)
#define DDR_REFRESH_PERIOD_SET(x)				(((x) << DDR_REFRESH_PERIOD_LSB) & DDR_REFRESH_PERIOD_MASK)
#define DDR_REFRESH_ADDRESS					0x18000014

// 0x18000018	DDR_RD_DATA_THIS_CYCLE
#define DDR_RD_DATA_THIS_CYCLE_VEC_MSB				31
#define DDR_RD_DATA_THIS_CYCLE_VEC_LSB				0
#define DDR_RD_DATA_THIS_CYCLE_VEC_MASK				0xffffffff
#define DDR_RD_DATA_THIS_CYCLE_VEC_GET(x)			(((x) & DDR_RD_DATA_THIS_CYCLE_VEC_MASK) >> DDR_RD_DATA_THIS_CYCLE_VEC_LSB)
#define DDR_RD_DATA_THIS_CYCLE_VEC_SET(x)			(((x) << DDR_RD_DATA_THIS_CYCLE_VEC_LSB) & DDR_RD_DATA_THIS_CYCLE_VEC_MASK)
#define DDR_RD_DATA_THIS_CYCLE_ADDRESS				0x18000018

// 0x1800001c	TAP_CONTROL_0
#define TAP_CONTROL_0_TAP_MSB					5
#define TAP_CONTROL_0_TAP_LSB					0
#define TAP_CONTROL_0_TAP_MASK					0x0000003f
#define TAP_CONTROL_0_TAP_GET(x)				(((x) & TAP_CONTROL_0_TAP_MASK) >> TAP_CONTROL_0_TAP_LSB)
#define TAP_CONTROL_0_TAP_SET(x)				(((x) << TAP_CONTROL_0_TAP_LSB) & TAP_CONTROL_0_TAP_MASK)
#define TAP_CONTROL_0_TAP_RESET					0x5 // 5
#define TAP_CONTROL_0_ADDRESS					0x1800001c

// 0x18000020	TAP_CONTROL_1
#define TAP_CONTROL_1_TAP_MSB					5
#define TAP_CONTROL_1_TAP_LSB					0
#define TAP_CONTROL_1_TAP_MASK					0x0000003f
#define TAP_CONTROL_1_TAP_GET(x)				(((x) & TAP_CONTROL_1_TAP_MASK) >> TAP_CONTROL_1_TAP_LSB)
#define TAP_CONTROL_1_TAP_SET(x)				(((x) << TAP_CONTROL_1_TAP_LSB) & TAP_CONTROL_1_TAP_MASK)
#define TAP_CONTROL_1_TAP_RESET					0x5 // 5
#define TAP_CONTROL_1_ADDRESS					0x18000020

// 0x18000024	TAP_CONTROL_2
#define TAP_CONTROL_2_TAP_MSB					5
#define TAP_CONTROL_2_TAP_LSB					0
#define TAP_CONTROL_2_TAP_MASK					0x0000003f
#define TAP_CONTROL_2_TAP_GET(x)				(((x) & TAP_CONTROL_2_TAP_MASK) >> TAP_CONTROL_2_TAP_LSB)
#define TAP_CONTROL_2_TAP_SET(x)				(((x) << TAP_CONTROL_2_TAP_LSB) & TAP_CONTROL_2_TAP_MASK)
#define TAP_CONTROL_2_TAP_RESET					0x5 // 5
#define TAP_CONTROL_2_ADDRESS					0x18000024

// 0x18000028	TAP_CONTROL_3
#define TAP_CONTROL_3_TAP_MSB					5
#define TAP_CONTROL_3_TAP_LSB					0
#define TAP_CONTROL_3_TAP_MASK					0x0000003f
#define TAP_CONTROL_3_TAP_GET(x)				(((x) & TAP_CONTROL_3_TAP_MASK) >> TAP_CONTROL_3_TAP_LSB)
#define TAP_CONTROL_3_TAP_SET(x)				(((x) << TAP_CONTROL_3_TAP_LSB) & TAP_CONTROL_3_TAP_MASK)
#define TAP_CONTROL_3_TAP_RESET					0x5 // 5
#define TAP_CONTROL_3_ADDRESS					0x18000028

// 0x180000b8	DDR2_CONFIG
#define DDR2_CONFIG_DDR2_TWL_MSB				13
#define DDR2_CONFIG_DDR2_TWL_LSB				10
#define DDR2_CONFIG_DDR2_TWL_MASK				0x00003c00
#define DDR2_CONFIG_DDR2_TWL_GET(x)				(((x) & DDR2_CONFIG_DDR2_TWL_MASK) >> DDR2_CONFIG_DDR2_TWL_LSB)
#define DDR2_CONFIG_DDR2_TWL_SET(x)				(((x) << DDR2_CONFIG_DDR2_TWL_LSB) & DDR2_CONFIG_DDR2_TWL_MASK)
#define DDR2_CONFIG_DDR2_TWL_RESET				0x1 // 1
#define DDR2_CONFIG_DDR2_ODT_MSB				9
#define DDR2_CONFIG_DDR2_ODT_LSB				9
#define DDR2_CONFIG_DDR2_ODT_MASK				0x00000200
#define DDR2_CONFIG_DDR2_ODT_GET(x)				(((x) & DDR2_CONFIG_DDR2_ODT_MASK) >> DDR2_CONFIG_DDR2_ODT_LSB)
#define DDR2_CONFIG_DDR2_ODT_SET(x)				(((x) << DDR2_CONFIG_DDR2_ODT_LSB) & DDR2_CONFIG_DDR2_ODT_MASK)
#define DDR2_CONFIG_DDR2_ODT_RESET				0x1 // 1
#define DDR2_CONFIG_TFAW_MSB					7
#define DDR2_CONFIG_TFAW_LSB					2
#define DDR2_CONFIG_TFAW_MASK					0x000000fc
#define DDR2_CONFIG_TFAW_GET(x)					(((x) & DDR2_CONFIG_TFAW_MASK) >> DDR2_CONFIG_TFAW_LSB)
#define DDR2_CONFIG_TFAW_SET(x)					(((x) << DDR2_CONFIG_TFAW_LSB) & DDR2_CONFIG_TFAW_MASK)
#define DDR2_CONFIG_ENABLE_DDR2_MSB				0
#define DDR2_CONFIG_ENABLE_DDR2_LSB				0
#define DDR2_CONFIG_ENABLE_DDR2_MASK				0x00000001
#define DDR2_CONFIG_ENABLE_DDR2_GET(x)				(((x) & DDR2_CONFIG_ENABLE_DDR2_MASK) >> DDR2_CONFIG_ENABLE_DDR2_LSB)
#define DDR2_CONFIG_ENABLE_DDR2_SET(x)				(((x) << DDR2_CONFIG_ENABLE_DDR2_LSB) & DDR2_CONFIG_ENABLE_DDR2_MASK)
#define DDR2_CONFIG_ENABLE_DDR2_RESET				0x0 // 0
#define DDR2_CONFIG_ADDRESS					0x180000b8

// 0x180000c4	DDR_BURST
#define DDR_BURST_CPU_PRIORITY_MSB				31
#define DDR_BURST_CPU_PRIORITY_LSB				31
#define DDR_BURST_CPU_PRIORITY_MASK				0x80000000
#define DDR_BURST_CPU_PRIORITY_GET(x)				(((x) & DDR_BURST_CPU_PRIORITY_MASK) >> DDR_BURST_CPU_PRIORITY_LSB)
#define DDR_BURST_CPU_PRIORITY_SET(x)				(((x) << DDR_BURST_CPU_PRIORITY_LSB) & DDR_BURST_CPU_PRIORITY_MASK)
#define DDR_BURST_CPU_PRIORITY_RESET				0x0 // 0
#define DDR_BURST_CPU_PRIORITY_BE_MSB				30
#define DDR_BURST_CPU_PRIORITY_BE_LSB				30
#define DDR_BURST_CPU_PRIORITY_BE_MASK				0x40000000
#define DDR_BURST_CPU_PRIORITY_BE_GET(x)			(((x) & DDR_BURST_CPU_PRIORITY_BE_MASK) >> DDR_BURST_CPU_PRIORITY_BE_LSB)
#define DDR_BURST_CPU_PRIORITY_BE_SET(x)			(((x) << DDR_BURST_CPU_PRIORITY_BE_LSB) & DDR_BURST_CPU_PRIORITY_BE_MASK)
#define DDR_BURST_CPU_PRIORITY_BE_RESET				0x1 // 1
#define DDR_BURST_ENABLE_RWP_MASK_MSB				29
#define DDR_BURST_ENABLE_RWP_MASK_LSB				28
#define DDR_BURST_ENABLE_RWP_MASK_MASK				0x30000000
#define DDR_BURST_ENABLE_RWP_MASK_GET(x)			(((x) & DDR_BURST_ENABLE_RWP_MASK_MASK) >> DDR_BURST_ENABLE_RWP_MASK_LSB)
#define DDR_BURST_ENABLE_RWP_MASK_SET(x)			(((x) << DDR_BURST_ENABLE_RWP_MASK_LSB) & DDR_BURST_ENABLE_RWP_MASK_MASK)
#define DDR_BURST_ENABLE_RWP_MASK_RESET				0x3 // 3
#define DDR_BURST_MAX_WRITE_BURST_MSB				27
#define DDR_BURST_MAX_WRITE_BURST_LSB				24
#define DDR_BURST_MAX_WRITE_BURST_MASK				0x0f000000
#define DDR_BURST_MAX_WRITE_BURST_GET(x)			(((x) & DDR_BURST_MAX_WRITE_BURST_MASK) >> DDR_BURST_MAX_WRITE_BURST_LSB)
#define DDR_BURST_MAX_WRITE_BURST_SET(x)			(((x) << DDR_BURST_MAX_WRITE_BURST_LSB) & DDR_BURST_MAX_WRITE_BURST_MASK)
#define DDR_BURST_MAX_WRITE_BURST_RESET				0x4 // 4
#define DDR_BURST_MAX_READ_BURST_MSB				23
#define DDR_BURST_MAX_READ_BURST_LSB				20
#define DDR_BURST_MAX_READ_BURST_MASK				0x00f00000
#define DDR_BURST_MAX_READ_BURST_GET(x)				(((x) & DDR_BURST_MAX_READ_BURST_MASK) >> DDR_BURST_MAX_READ_BURST_LSB)
#define DDR_BURST_MAX_READ_BURST_SET(x)				(((x) << DDR_BURST_MAX_READ_BURST_LSB) & DDR_BURST_MAX_READ_BURST_MASK)
#define DDR_BURST_MAX_READ_BURST_RESET				0x4 // 4
#define DDR_BURST_CPU_MAX_BL_MSB				19
#define DDR_BURST_CPU_MAX_BL_LSB				16
#define DDR_BURST_CPU_MAX_BL_MASK				0x000f0000
#define DDR_BURST_CPU_MAX_BL_GET(x)				(((x) & DDR_BURST_CPU_MAX_BL_MASK) >> DDR_BURST_CPU_MAX_BL_LSB)
#define DDR_BURST_CPU_MAX_BL_SET(x)				(((x) << DDR_BURST_CPU_MAX_BL_LSB) & DDR_BURST_CPU_MAX_BL_MASK)
#define DDR_BURST_CPU_MAX_BL_RESET				0x3 // 3
#define DDR_BURST_USB_MAX_BL_MSB				15
#define DDR_BURST_USB_MAX_BL_LSB				12
#define DDR_BURST_USB_MAX_BL_MASK				0x0000f000
#define DDR_BURST_USB_MAX_BL_GET(x)				(((x) & DDR_BURST_USB_MAX_BL_MASK) >> DDR_BURST_USB_MAX_BL_LSB)
#define DDR_BURST_USB_MAX_BL_SET(x)				(((x) << DDR_BURST_USB_MAX_BL_LSB) & DDR_BURST_USB_MAX_BL_MASK)
#define DDR_BURST_USB_MAX_BL_RESET				0x4 // 4
#define DDR_BURST_PCIE_MAX_BL_MSB				11
#define DDR_BURST_PCIE_MAX_BL_LSB				8
#define DDR_BURST_PCIE_MAX_BL_MASK				0x00000f00
#define DDR_BURST_PCIE_MAX_BL_GET(x)				(((x) & DDR_BURST_PCIE_MAX_BL_MASK) >> DDR_BURST_PCIE_MAX_BL_LSB)
#define DDR_BURST_PCIE_MAX_BL_SET(x)				(((x) << DDR_BURST_PCIE_MAX_BL_LSB) & DDR_BURST_PCIE_MAX_BL_MASK)
#define DDR_BURST_PCIE_MAX_BL_RESET				0x3 // 3
#define DDR_BURST_GE1_MAX_BL_MSB				7
#define DDR_BURST_GE1_MAX_BL_LSB				4
#define DDR_BURST_GE1_MAX_BL_MASK				0x000000f0
#define DDR_BURST_GE1_MAX_BL_GET(x)				(((x) & DDR_BURST_GE1_MAX_BL_MASK) >> DDR_BURST_GE1_MAX_BL_LSB)
#define DDR_BURST_GE1_MAX_BL_SET(x)				(((x) << DDR_BURST_GE1_MAX_BL_LSB) & DDR_BURST_GE1_MAX_BL_MASK)
#define DDR_BURST_GE1_MAX_BL_RESET				0x3 // 3
#define DDR_BURST_GE0_MAX_BL_MSB				3
#define DDR_BURST_GE0_MAX_BL_LSB				0
#define DDR_BURST_GE0_MAX_BL_MASK				0x0000000f
#define DDR_BURST_GE0_MAX_BL_GET(x)				(((x) & DDR_BURST_GE0_MAX_BL_MASK) >> DDR_BURST_GE0_MAX_BL_LSB)
#define DDR_BURST_GE0_MAX_BL_SET(x)				(((x) << DDR_BURST_GE0_MAX_BL_LSB) & DDR_BURST_GE0_MAX_BL_MASK)
#define DDR_BURST_GE0_MAX_BL_RESET				0x3 // 3
#define DDR_BURST_ADDRESS					0x180000c4

// 0x180000c8	DDR_BURST2
#define DDR_BURST2_MISC_SRC2_MAX_BL_MSB				11
#define DDR_BURST2_MISC_SRC2_MAX_BL_LSB				8
#define DDR_BURST2_MISC_SRC2_MAX_BL_MASK			0x00000f00
#define DDR_BURST2_MISC_SRC2_MAX_BL_GET(x)			(((x) & DDR_BURST2_MISC_SRC2_MAX_BL_MASK) >> DDR_BURST2_MISC_SRC2_MAX_BL_LSB)
#define DDR_BURST2_MISC_SRC2_MAX_BL_SET(x)			(((x) << DDR_BURST2_MISC_SRC2_MAX_BL_LSB) & DDR_BURST2_MISC_SRC2_MAX_BL_MASK)
#define DDR_BURST2_MISC_SRC2_MAX_BL_RESET			0x2 // 2
#define DDR_BURST2_MISC_SRC1_MAX_BL_MSB				7
#define DDR_BURST2_MISC_SRC1_MAX_BL_LSB				4
#define DDR_BURST2_MISC_SRC1_MAX_BL_MASK			0x000000f0
#define DDR_BURST2_MISC_SRC1_MAX_BL_GET(x)			(((x) & DDR_BURST2_MISC_SRC1_MAX_BL_MASK) >> DDR_BURST2_MISC_SRC1_MAX_BL_LSB)
#define DDR_BURST2_MISC_SRC1_MAX_BL_SET(x)			(((x) << DDR_BURST2_MISC_SRC1_MAX_BL_LSB) & DDR_BURST2_MISC_SRC1_MAX_BL_MASK)
#define DDR_BURST2_MISC_SRC1_MAX_BL_RESET			0x2 // 2
#define DDR_BURST2_WMAC_MAX_BL_MSB				3
#define DDR_BURST2_WMAC_MAX_BL_LSB				0
#define DDR_BURST2_WMAC_MAX_BL_MASK				0x0000000f
#define DDR_BURST2_WMAC_MAX_BL_GET(x)				(((x) & DDR_BURST2_WMAC_MAX_BL_MASK) >> DDR_BURST2_WMAC_MAX_BL_LSB)
#define DDR_BURST2_WMAC_MAX_BL_SET(x)				(((x) << DDR_BURST2_WMAC_MAX_BL_LSB) & DDR_BURST2_WMAC_MAX_BL_MASK)
#define DDR_BURST2_WMAC_MAX_BL_RESET				0x3 // 3
#define DDR_BURST2_ADDRESS					0x180000c8

// 0x180000cc	DDR_AHB_MASTER_TIMEOUT_MAX
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MSB			19
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB			0
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK			0x000fffff
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_GET(x)			(((x) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK) >> DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB)
#define DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_SET(x)			(((x) << DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_LSB) & DDR_AHB_MASTER_TIMEOUT_MAX_VALUE_MASK)
#define DDR_AHB_MASTER_TIMEOUT_MAX_ADDRESS			0x180000cc

// 0x18000108	DDR_CTL_CONFIG
#define DDR_CTL_CONFIG_SRAM_TSEL_MSB				31
#define DDR_CTL_CONFIG_SRAM_TSEL_LSB				30
#define DDR_CTL_CONFIG_SRAM_TSEL_MASK				0xc0000000
#define DDR_CTL_CONFIG_SRAM_TSEL_GET(x)				(((x) & DDR_CTL_CONFIG_SRAM_TSEL_MASK) >> DDR_CTL_CONFIG_SRAM_TSEL_LSB)
#define DDR_CTL_CONFIG_SRAM_TSEL_SET(x)				(((x) << DDR_CTL_CONFIG_SRAM_TSEL_LSB) & DDR_CTL_CONFIG_SRAM_TSEL_MASK)
#define DDR_CTL_CONFIG_SRAM_TSEL_RESET				0x1 // 1
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MSB			29
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB			21
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK			0x3fe00000
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_GET(x)			(((x) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK) >> DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_SET(x)			(((x) << DDR_CTL_CONFIG_CLIENT_ACTIVITY_LSB) & DDR_CTL_CONFIG_CLIENT_ACTIVITY_MASK)
#define DDR_CTL_CONFIG_CLIENT_ACTIVITY_RESET			0x0 // 0
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MSB			20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB			20
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK			0x00100000
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_GE0_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE0_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE0_SRAM_SYNC_RESET			0x1 // 1
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MSB			19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB			19
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK			0x00080000
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_GE1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_GE1_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_GE1_SRAM_SYNC_RESET			0x1 // 1
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MSB			18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB			18
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK			0x00040000
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_USB_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_USB_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_USB_SRAM_SYNC_RESET			0x1 // 1
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MSB			17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB			17
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK			0x00020000
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_PCIE_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_PCIE_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_PCIE_SRAM_SYNC_RESET			0x1 // 1
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MSB			16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB			16
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK			0x00010000
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_WMAC_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_WMAC_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_WMAC_SRAM_SYNC_RESET			0x1 // 1
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MSB			15
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB			15
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK			0x00008000
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_GET(x)		(((x) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(x)		(((x) << DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_RESET		0x1 // 1
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MSB			14
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB			14
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK			0x00004000
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_GET(x)		(((x) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK) >> DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB)
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(x)		(((x) << DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_LSB) & DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_MASK)
#define DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_RESET		0x1 // 1
#define DDR_CTL_CONFIG_SPARE_MSB				13
#define DDR_CTL_CONFIG_SPARE_LSB				7
#define DDR_CTL_CONFIG_SPARE_MASK				0x00003f80
#define DDR_CTL_CONFIG_SPARE_GET(x)				(((x) & DDR_CTL_CONFIG_SPARE_MASK) >> DDR_CTL_CONFIG_SPARE_LSB)
#define DDR_CTL_CONFIG_SPARE_SET(x)				(((x) << DDR_CTL_CONFIG_SPARE_LSB) & DDR_CTL_CONFIG_SPARE_MASK)
#define DDR_CTL_CONFIG_SPARE_RESET				0x0 // 0
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MSB				6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB				6
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK			0x00000040
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_GET(x)			(((x) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK) >> DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_SET(x)			(((x) << DDR_CTL_CONFIG_PAD_DDR2_SEL_LSB) & DDR_CTL_CONFIG_PAD_DDR2_SEL_MASK)
#define DDR_CTL_CONFIG_PAD_DDR2_SEL_RESET			0x0 // 0
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MSB			4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB			4
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK			0x00000010
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_GET(x)			(((x) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK) >> DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_SET(x)			(((x) << DDR_CTL_CONFIG_GATE_SRAM_CLK_LSB) & DDR_CTL_CONFIG_GATE_SRAM_CLK_MASK)
#define DDR_CTL_CONFIG_GATE_SRAM_CLK_RESET			0x0 // 0
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MSB				3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB				3
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK			0x00000008
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_GET(x)			(((x) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK) >> DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_SET(x)			(((x) << DDR_CTL_CONFIG_SRAM_REQ_ACK_LSB) & DDR_CTL_CONFIG_SRAM_REQ_ACK_MASK)
#define DDR_CTL_CONFIG_SRAM_REQ_ACK_RESET			0x0 // 0
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MSB				2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB				2
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK			0x00000004
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_GET(x)			(((x) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK) >> DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_SET(x)			(((x) << DDR_CTL_CONFIG_CPU_DDR_SYNC_LSB) & DDR_CTL_CONFIG_CPU_DDR_SYNC_MASK)
#define DDR_CTL_CONFIG_CPU_DDR_SYNC_RESET			0x0 // 0
#define DDR_CTL_CONFIG_HALF_WIDTH_MSB				1
#define DDR_CTL_CONFIG_HALF_WIDTH_LSB				1
#define DDR_CTL_CONFIG_HALF_WIDTH_MASK				0x00000002
#define DDR_CTL_CONFIG_HALF_WIDTH_GET(x)			(((x) & DDR_CTL_CONFIG_HALF_WIDTH_MASK) >> DDR_CTL_CONFIG_HALF_WIDTH_LSB)
#define DDR_CTL_CONFIG_HALF_WIDTH_SET(x)			(((x) << DDR_CTL_CONFIG_HALF_WIDTH_LSB) & DDR_CTL_CONFIG_HALF_WIDTH_MASK)
#define DDR_CTL_CONFIG_HALF_WIDTH_RESET				0x1 // 1
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MSB			0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB			0
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK			0x00000001
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_GET(x)			(((x) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK) >> DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_SET(x)			(((x) << DDR_CTL_CONFIG_SDRAM_MODE_EN_LSB) & DDR_CTL_CONFIG_SDRAM_MODE_EN_MASK)
#define DDR_CTL_CONFIG_SDRAM_MODE_EN_RESET			0x0 // 0
#define DDR_CTL_CONFIG_ADDRESS					0x18000108

// 0x18040000	GPIO_OE
#define GPIO_OE_OE_MSB						31
#define GPIO_OE_OE_LSB						0
#define GPIO_OE_OE_MASK						0xffffffff
#define GPIO_OE_OE_GET(x)					(((x) & GPIO_OE_OE_MASK) >> GPIO_OE_OE_LSB)
#define GPIO_OE_OE_SET(x)					(((x) << GPIO_OE_OE_LSB) & GPIO_OE_OE_MASK)
#define GPIO_OE_ADDRESS						0x18040000

// 0x18041000	P_GPIO_OE
#define P_GPIO_OE_OE_MSB					31
#define P_GPIO_OE_OE_LSB					0
#define P_GPIO_OE_OE_MASK					0xffffffff
#define P_GPIO_OE_OE_GET(x)					(((x) & P_GPIO_OE_OE_MASK) >> P_GPIO_OE_OE_LSB)
#define P_GPIO_OE_OE_SET(x)					(((x) << P_GPIO_OE_OE_LSB) & P_GPIO_OE_OE_MASK)
#define P_GPIO_OE_OE_RESET					0x0 // 0
#define P_GPIO_OE_ADDRESS					0x18041000

// 0x18040004	GPIO_IN
#define GPIO_IN_IN_MSB						31
#define GPIO_IN_IN_LSB						0
#define GPIO_IN_IN_MASK						0xffffffff
#define GPIO_IN_IN_GET(x)					(((x) & GPIO_IN_IN_MASK) >> GPIO_IN_IN_LSB)
#define GPIO_IN_IN_SET(x)					(((x) << GPIO_IN_IN_LSB) & GPIO_IN_IN_MASK)
#define GPIO_IN_IN_RESET					0x0 // 0
#define GPIO_IN_ADDRESS						0x18040004

// 0x18041004	P_GPIO_IN
#define P_GPIO_IN_IN_MSB					31
#define P_GPIO_IN_IN_LSB					0
#define P_GPIO_IN_IN_MASK					0xffffffff
#define P_GPIO_IN_IN_GET(x)					(((x) & P_GPIO_IN_IN_MASK) >> P_GPIO_IN_IN_LSB)
#define P_GPIO_IN_IN_SET(x)					(((x) << P_GPIO_IN_IN_LSB) & P_GPIO_IN_IN_MASK)
#define P_GPIO_IN_IN_RESET					0x0 // 0
#define P_GPIO_IN_ADDRESS					0x18041004

// 0x1810404c	WMAC_GLUE_INTF_GPIO_IN
#define WMAC_GLUE_INTF_GPIO_IN_IN_MSB				10
#define WMAC_GLUE_INTF_GPIO_IN_IN_LSB				0
#define WMAC_GLUE_INTF_GPIO_IN_IN_MASK				0x000007ff
#define WMAC_GLUE_INTF_GPIO_IN_IN_GET(x)			(((x) & WMAC_GLUE_INTF_GPIO_IN_IN_MASK) >> WMAC_GLUE_INTF_GPIO_IN_IN_LSB)
#define WMAC_GLUE_INTF_GPIO_IN_IN_SET(x)			(((x) << WMAC_GLUE_INTF_GPIO_IN_IN_LSB) & WMAC_GLUE_INTF_GPIO_IN_IN_MASK)
#define WMAC_GLUE_INTF_GPIO_IN_IN_RESET				0x0 // 0
#define WMAC_GLUE_INTF_GPIO_IN_ADDRESS				0x1810404c

// 0x18040008	GPIO_OUT
#define GPIO_OUT_OUT_MSB					31
#define GPIO_OUT_OUT_LSB					0
#define GPIO_OUT_OUT_MASK					0xffffffff
#define GPIO_OUT_OUT_GET(x)					(((x) & GPIO_OUT_OUT_MASK) >> GPIO_OUT_OUT_LSB)
#define GPIO_OUT_OUT_SET(x)					(((x) << GPIO_OUT_OUT_LSB) & GPIO_OUT_OUT_MASK)
#define GPIO_OUT_OUT_RESET					0x0 // 0
#define GPIO_OUT_ADDRESS					0x18040008

// 0x18041008	P_GPIO_OUT
#define P_GPIO_OUT_OUT_MSB					31
#define P_GPIO_OUT_OUT_LSB					0
#define P_GPIO_OUT_OUT_MASK					0xffffffff
#define P_GPIO_OUT_OUT_GET(x)					(((x) & P_GPIO_OUT_OUT_MASK) >> P_GPIO_OUT_OUT_LSB)
#define P_GPIO_OUT_OUT_SET(x)					(((x) << P_GPIO_OUT_OUT_LSB) & P_GPIO_OUT_OUT_MASK)
#define P_GPIO_OUT_OUT_RESET					0x0 // 0
#define P_GPIO_OUT_ADDRESS					0x18041008

// 0x18104048	WMAC_GLUE_INTF_GPIO_OUT
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_MSB				3
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_LSB				0
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_MASK			0x0000000f
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_GET(x)			(((x) & WMAC_GLUE_INTF_GPIO_OUT_OUT_MASK) >> WMAC_GLUE_INTF_GPIO_OUT_OUT_LSB)
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_SET(x)			(((x) << WMAC_GLUE_INTF_GPIO_OUT_OUT_LSB) & WMAC_GLUE_INTF_GPIO_OUT_OUT_MASK)
#define WMAC_GLUE_INTF_GPIO_OUT_OUT_RESET			0x0 // 0
#define WMAC_GLUE_INTF_GPIO_OUT_ADDRESS				0x18104048

// 0x1804000c	GPIO_SET
#define GPIO_SET_SET_MSB					31
#define GPIO_SET_SET_LSB					0
#define GPIO_SET_SET_MASK					0xffffffff
#define GPIO_SET_SET_GET(x)					(((x) & GPIO_SET_SET_MASK) >> GPIO_SET_SET_LSB)
#define GPIO_SET_SET_SET(x)					(((x) << GPIO_SET_SET_LSB) & GPIO_SET_SET_MASK)
#define GPIO_SET_SET_RESET					0x0 // 0
#define GPIO_SET_ADDRESS					0x1804000c

// 0x1804100c	P_GPIO_SET
#define P_GPIO_SET_SET_MSB					31
#define P_GPIO_SET_SET_LSB					0
#define P_GPIO_SET_SET_MASK					0xffffffff
#define P_GPIO_SET_SET_GET(x)					(((x) & P_GPIO_SET_SET_MASK) >> P_GPIO_SET_SET_LSB)
#define P_GPIO_SET_SET_SET(x)					(((x) << P_GPIO_SET_SET_LSB) & P_GPIO_SET_SET_MASK)
#define P_GPIO_SET_SET_RESET					0x0 // 0
#define P_GPIO_SET_ADDRESS					0x1804100c

// 0x18040010	GPIO_CLEAR
#define GPIO_CLEAR_CLEAR_MSB					31
#define GPIO_CLEAR_CLEAR_LSB					0
#define GPIO_CLEAR_CLEAR_MASK					0xffffffff
#define GPIO_CLEAR_CLEAR_GET(x)					(((x) & GPIO_CLEAR_CLEAR_MASK) >> GPIO_CLEAR_CLEAR_LSB)
#define GPIO_CLEAR_CLEAR_SET(x)					(((x) << GPIO_CLEAR_CLEAR_LSB) & GPIO_CLEAR_CLEAR_MASK)
#define GPIO_CLEAR_CLEAR_RESET					0x0 // 0
#define GPIO_CLEAR_ADDRESS					0x18040010

// 0x18041010	P_GPIO_CLEAR
#define P_GPIO_CLEAR_CLEAR_MSB					31
#define P_GPIO_CLEAR_CLEAR_LSB					0
#define P_GPIO_CLEAR_CLEAR_MASK					0xffffffff
#define P_GPIO_CLEAR_CLEAR_GET(x)				(((x) & P_GPIO_CLEAR_CLEAR_MASK) >> P_GPIO_CLEAR_CLEAR_LSB)
#define P_GPIO_CLEAR_CLEAR_SET(x)				(((x) << P_GPIO_CLEAR_CLEAR_LSB) & P_GPIO_CLEAR_CLEAR_MASK)
#define P_GPIO_CLEAR_CLEAR_RESET				0x0 // 0
#define P_GPIO_CLEAR_ADDRESS					0x18041010

// 0x18040014	GPIO_INT
#define GPIO_INT_INT_MSB					31
#define GPIO_INT_INT_LSB					0
#define GPIO_INT_INT_MASK					0xffffffff
#define GPIO_INT_INT_GET(x)					(((x) & GPIO_INT_INT_MASK) >> GPIO_INT_INT_LSB)
#define GPIO_INT_INT_SET(x)					(((x) << GPIO_INT_INT_LSB) & GPIO_INT_INT_MASK)
#define GPIO_INT_INT_RESET					0x0 // 0
#define GPIO_INT_ADDRESS					0x18040014

// 0x18041014	P_GPIO_INT
#define P_GPIO_INT_INT_MSB					31
#define P_GPIO_INT_INT_LSB					0
#define P_GPIO_INT_INT_MASK					0xffffffff
#define P_GPIO_INT_INT_GET(x)					(((x) & P_GPIO_INT_INT_MASK) >> P_GPIO_INT_INT_LSB)
#define P_GPIO_INT_INT_SET(x)					(((x) << P_GPIO_INT_INT_LSB) & P_GPIO_INT_INT_MASK)
#define P_GPIO_INT_INT_RESET					0x0 // 0
#define P_GPIO_INT_ADDRESS					0x18041014

// 0x18040018	GPIO_INT_TYPE
#define GPIO_INT_TYPE_TYPE_MSB					31
#define GPIO_INT_TYPE_TYPE_LSB					0
#define GPIO_INT_TYPE_TYPE_MASK					0xffffffff
#define GPIO_INT_TYPE_TYPE_GET(x)				(((x) & GPIO_INT_TYPE_TYPE_MASK) >> GPIO_INT_TYPE_TYPE_LSB)
#define GPIO_INT_TYPE_TYPE_SET(x)				(((x) << GPIO_INT_TYPE_TYPE_LSB) & GPIO_INT_TYPE_TYPE_MASK)
#define GPIO_INT_TYPE_TYPE_RESET				0x0 // 0
#define GPIO_INT_TYPE_ADDRESS					0x18040018

// 0x18041018	P_GPIO_INT_TYPE
#define P_GPIO_INT_TYPE_TYPE_MSB				31
#define P_GPIO_INT_TYPE_TYPE_LSB				0
#define P_GPIO_INT_TYPE_TYPE_MASK				0xffffffff
#define P_GPIO_INT_TYPE_TYPE_GET(x)				(((x) & P_GPIO_INT_TYPE_TYPE_MASK) >> P_GPIO_INT_TYPE_TYPE_LSB)
#define P_GPIO_INT_TYPE_TYPE_SET(x)				(((x) << P_GPIO_INT_TYPE_TYPE_LSB) & P_GPIO_INT_TYPE_TYPE_MASK)
#define P_GPIO_INT_TYPE_TYPE_RESET				0x0 // 0
#define P_GPIO_INT_TYPE_ADDRESS					0x18041018

// 0x1804001c	GPIO_INT_POLARITY
#define GPIO_INT_POLARITY_POLARITY_MSB				31
#define GPIO_INT_POLARITY_POLARITY_LSB				0
#define GPIO_INT_POLARITY_POLARITY_MASK				0xffffffff
#define GPIO_INT_POLARITY_POLARITY_GET(x)			(((x) & GPIO_INT_POLARITY_POLARITY_MASK) >> GPIO_INT_POLARITY_POLARITY_LSB)
#define GPIO_INT_POLARITY_POLARITY_SET(x)			(((x) << GPIO_INT_POLARITY_POLARITY_LSB) & GPIO_INT_POLARITY_POLARITY_MASK)
#define GPIO_INT_POLARITY_POLARITY_RESET			0x0 // 0
#define GPIO_INT_POLARITY_ADDRESS				0x1804001c

// 0x1804101c	P_GPIO_INT_POLARITY
#define P_GPIO_INT_POLARITY_POLARITY_MSB			31
#define P_GPIO_INT_POLARITY_POLARITY_LSB			0
#define P_GPIO_INT_POLARITY_POLARITY_MASK			0xffffffff
#define P_GPIO_INT_POLARITY_POLARITY_GET(x)			(((x) & P_GPIO_INT_POLARITY_POLARITY_MASK) >> P_GPIO_INT_POLARITY_POLARITY_LSB)
#define P_GPIO_INT_POLARITY_POLARITY_SET(x)			(((x) << P_GPIO_INT_POLARITY_POLARITY_LSB) & P_GPIO_INT_POLARITY_POLARITY_MASK)
#define P_GPIO_INT_POLARITY_POLARITY_RESET			0x0 // 0
#define P_GPIO_INT_POLARITY_ADDRESS				0x1804101c

// 0x18040020	GPIO_INT_PENDING
#define GPIO_INT_PENDING_PENDING_MSB				31
#define GPIO_INT_PENDING_PENDING_LSB				0
#define GPIO_INT_PENDING_PENDING_MASK				0xffffffff
#define GPIO_INT_PENDING_PENDING_GET(x)				(((x) & GPIO_INT_PENDING_PENDING_MASK) >> GPIO_INT_PENDING_PENDING_LSB)
#define GPIO_INT_PENDING_PENDING_SET(x)				(((x) << GPIO_INT_PENDING_PENDING_LSB) & GPIO_INT_PENDING_PENDING_MASK)
#define GPIO_INT_PENDING_PENDING_RESET				0x0 // 0
#define GPIO_INT_PENDING_ADDRESS				0x18040020

// 0x18041020	P_GPIO_INT_PENDING
#define P_GPIO_INT_PENDING_PENDING_MSB				31
#define P_GPIO_INT_PENDING_PENDING_LSB				0
#define P_GPIO_INT_PENDING_PENDING_MASK				0xffffffff
#define P_GPIO_INT_PENDING_PENDING_GET(x)			(((x) & P_GPIO_INT_PENDING_PENDING_MASK) >> P_GPIO_INT_PENDING_PENDING_LSB)
#define P_GPIO_INT_PENDING_PENDING_SET(x)			(((x) << P_GPIO_INT_PENDING_PENDING_LSB) & P_GPIO_INT_PENDING_PENDING_MASK)
#define P_GPIO_INT_PENDING_PENDING_RESET			0x0 // 0
#define P_GPIO_INT_PENDING_ADDRESS				0x18041020

// 0x18040024	GPIO_INT_MASK
#define GPIO_INT_MASK_MASK_MSB					31
#define GPIO_INT_MASK_MASK_LSB					0
#define GPIO_INT_MASK_MASK_MASK					0xffffffff
#define GPIO_INT_MASK_MASK_GET(x)				(((x) & GPIO_INT_MASK_MASK_MASK) >> GPIO_INT_MASK_MASK_LSB)
#define GPIO_INT_MASK_MASK_SET(x)				(((x) << GPIO_INT_MASK_MASK_LSB) & GPIO_INT_MASK_MASK_MASK)
#define GPIO_INT_MASK_MASK_RESET				0x0 // 0
#define GPIO_INT_MASK_ADDRESS					0x18040024

// 0x18041024	P_GPIO_INT_MASK
#define P_GPIO_INT_MASK_MASK_MSB				31
#define P_GPIO_INT_MASK_MASK_LSB				0
#define P_GPIO_INT_MASK_MASK_MASK				0xffffffff
#define P_GPIO_INT_MASK_MASK_GET(x)				(((x) & P_GPIO_INT_MASK_MASK_MASK) >> P_GPIO_INT_MASK_MASK_LSB)
#define P_GPIO_INT_MASK_MASK_SET(x)				(((x) << P_GPIO_INT_MASK_MASK_LSB) & P_GPIO_INT_MASK_MASK_MASK)
#define P_GPIO_INT_MASK_MASK_RESET				0x0 // 0
#define P_GPIO_INT_MASK_ADDRESS					0x18041024

// 0x18040028	GPIO_SPARE
#define GPIO_SPARE_BITS_MSB					31
#define GPIO_SPARE_BITS_LSB					0
#define GPIO_SPARE_BITS_MASK					0xffffffff
#define GPIO_SPARE_BITS_GET(x)					(((x) & GPIO_SPARE_BITS_MASK) >> GPIO_SPARE_BITS_LSB)
#define GPIO_SPARE_BITS_SET(x)					(((x) << GPIO_SPARE_BITS_LSB) & GPIO_SPARE_BITS_MASK)
#define GPIO_SPARE_BITS_RESET					0x0 // 0
#define GPIO_SPARE_ADDRESS					0x18040028

// 0x1804002c	GPIO_OUT_FUNCTION0
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MSB			31
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB			24
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK			0xff000000
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_GET(x)			(((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_SET(x)			(((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_MASK)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_3_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MSB			23
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB			16
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_GET(x)			(((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_SET(x)			(((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_MASK)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_2_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MSB			15
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB			8
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_GET(x)			(((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_SET(x)			(((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_MASK)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_1_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MSB			7
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB			0
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK			0x000000ff
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_GET(x)			(((x) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK) >> GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_SET(x)			(((x) << GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_LSB) & GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_MASK)
#define GPIO_OUT_FUNCTION0_ENABLE_GPIO_0_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION0_ADDRESS				0x1804002c

// 0x18040030	GPIO_OUT_FUNCTION1
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MSB			31
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB			24
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK			0xff000000
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_GET(x)			(((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_SET(x)			(((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_7_RESET			0xc // 12
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MSB			23
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB			16
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_GET(x)			(((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_SET(x)			(((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_6_RESET			0x8 // 8
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MSB			15
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB			8
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_GET(x)			(((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_SET(x)			(((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_MASK)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_5_RESET			0x9 // 9
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MSB			7
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB			0
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK			0x000000ff
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_GET(x)			(((x) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK) >> GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB)
#define GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_SET(x)			(((x) << GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_LSB) & GPIO_OUT_FUNCTION1_ENABLE_GPIO_4_MASK)
#define GPIO_OUT_FUNCTION1_ADDRESS				0x18040030

// 0x18040034	GPIO_OUT_FUNCTION2
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MSB			31
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB			24
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK			0xff000000
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_GET(x)		(((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_SET(x)		(((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_11_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MSB			23
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB			16
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_GET(x)		(((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(x)		(((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MSB			15
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB			8
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_GET(x)			(((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_SET(x)			(((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_9_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MSB			7
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB			0
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK			0x000000ff
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_GET(x)			(((x) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK) >> GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_SET(x)			(((x) << GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_LSB) & GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_MASK)
#define GPIO_OUT_FUNCTION2_ENABLE_GPIO_8_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION2_ADDRESS				0x18040034

// 0x18040038	GPIO_OUT_FUNCTION3
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MSB			31
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB			24
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK			0xff000000
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_GET(x)		(((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_SET(x)		(((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_MASK)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_15_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MSB			23
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB			16
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_GET(x)		(((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_SET(x)		(((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_MASK)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_14_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MSB			15
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB			8
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_GET(x)		(((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(x)		(((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MSB			7
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB			0
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK			0x000000ff
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_GET(x)		(((x) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK) >> GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_SET(x)		(((x) << GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_LSB) & GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_MASK)
#define GPIO_OUT_FUNCTION3_ENABLE_GPIO_12_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION3_ADDRESS				0x18040038

// 0x1804003c	GPIO_OUT_FUNCTION4
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MSB			31
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB			24
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK			0xff000000
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_GET(x)		(((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_SET(x)		(((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_MASK)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_19_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MSB			23
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB			16
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_GET(x)		(((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_SET(x)		(((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MSB			15
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB			8
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_GET(x)		(((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_SET(x)		(((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_MASK)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_17_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MSB			7
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB			0
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK			0x000000ff
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_GET(x)		(((x) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK) >> GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_SET(x)		(((x) << GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_LSB) & GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_MASK)
#define GPIO_OUT_FUNCTION4_ENABLE_GPIO_16_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION4_ADDRESS				0x1804003c

// 0x18040040	GPIO_OUT_FUNCTION5
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_MSB			31
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_LSB			24
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_MASK			0xff000000
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_GET(x)		(((x) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_MASK) >> GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_LSB)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_SET(x)		(((x) << GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_LSB) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_MASK)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_23_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MSB			23
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_LSB			16
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK			0x00ff0000
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_GET(x)		(((x) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK) >> GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_LSB)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(x)		(((x) << GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_LSB) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MSB			15
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_LSB			8
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MASK			0x0000ff00
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_GET(x)		(((x) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MASK) >> GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_LSB)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_SET(x)		(((x) << GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_LSB) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_MASK)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_21_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MSB			7
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_LSB			0
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK			0x000000ff
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_GET(x)		(((x) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK) >> GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_LSB)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(x)		(((x) << GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_LSB) & GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK)
#define GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_RESET			0x0 // 0
#define GPIO_OUT_FUNCTION5_ADDRESS				0x18040040

// 0x18040044	GPIO_IN_ENABLE0
#define GPIO_IN_ENABLE0_UART_SIN_MSB				15
#define GPIO_IN_ENABLE0_UART_SIN_LSB				8
#define GPIO_IN_ENABLE0_UART_SIN_MASK				0x0000ff00
#define GPIO_IN_ENABLE0_UART_SIN_GET(x)				(((x) & GPIO_IN_ENABLE0_UART_SIN_MASK) >> GPIO_IN_ENABLE0_UART_SIN_LSB)
#define GPIO_IN_ENABLE0_UART_SIN_SET(x)				(((x) << GPIO_IN_ENABLE0_UART_SIN_LSB) & GPIO_IN_ENABLE0_UART_SIN_MASK)
#define GPIO_IN_ENABLE0_SPI_DATA_IN_MSB				7
#define GPIO_IN_ENABLE0_SPI_DATA_IN_LSB				0
#define GPIO_IN_ENABLE0_SPI_DATA_IN_MASK			0x000000ff
#define GPIO_IN_ENABLE0_SPI_DATA_IN_GET(x)			(((x) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK) >> GPIO_IN_ENABLE0_SPI_DATA_IN_LSB)
#define GPIO_IN_ENABLE0_SPI_DATA_IN_SET(x)			(((x) << GPIO_IN_ENABLE0_SPI_DATA_IN_LSB) & GPIO_IN_ENABLE0_SPI_DATA_IN_MASK)
#define GPIO_IN_ENABLE0_SPI_DATA_IN_RESET			0x8 // 8
#define GPIO_IN_ENABLE0_ADDRESS					0x18040044

// 0x18040048	GPIO_IN_ENABLE1
#define GPIO_IN_ENABLE1_I2SEXT_MCLK_MSB				31
#define GPIO_IN_ENABLE1_I2SEXT_MCLK_LSB				24
#define GPIO_IN_ENABLE1_I2SEXT_MCLK_MASK			0xff000000
#define GPIO_IN_ENABLE1_I2SEXT_MCLK_GET(x)			(((x) & GPIO_IN_ENABLE1_I2SEXT_MCLK_MASK) >> GPIO_IN_ENABLE1_I2SEXT_MCLK_LSB)
#define GPIO_IN_ENABLE1_I2SEXT_MCLK_SET(x)			(((x) << GPIO_IN_ENABLE1_I2SEXT_MCLK_LSB) & GPIO_IN_ENABLE1_I2SEXT_MCLK_MASK)
#define GPIO_IN_ENABLE1_I2SEXTCLK_MSB				23
#define GPIO_IN_ENABLE1_I2SEXTCLK_LSB				16
#define GPIO_IN_ENABLE1_I2SEXTCLK_MASK				0x00ff0000
#define GPIO_IN_ENABLE1_I2SEXTCLK_GET(x)			(((x) & GPIO_IN_ENABLE1_I2SEXTCLK_MASK) >> GPIO_IN_ENABLE1_I2SEXTCLK_LSB)
#define GPIO_IN_ENABLE1_I2SEXTCLK_SET(x)			(((x) << GPIO_IN_ENABLE1_I2SEXTCLK_LSB) & GPIO_IN_ENABLE1_I2SEXTCLK_MASK)
#define GPIO_IN_ENABLE1_I2S0__MIC_SD_MSB			15
#define GPIO_IN_ENABLE1_I2S0__MIC_SD_LSB			8
#define GPIO_IN_ENABLE1_I2S0__MIC_SD_MASK			0x0000ff00
#define GPIO_IN_ENABLE1_I2S0__MIC_SD_GET(x)			(((x) & GPIO_IN_ENABLE1_I2S0__MIC_SD_MASK) >> GPIO_IN_ENABLE1_I2S0__MIC_SD_LSB)
#define GPIO_IN_ENABLE1_I2S0__MIC_SD_SET(x)			(((x) << GPIO_IN_ENABLE1_I2S0__MIC_SD_LSB) & GPIO_IN_ENABLE1_I2S0__MIC_SD_MASK)
#define GPIO_IN_ENABLE1_I2S0__WS_MSB				7
#define GPIO_IN_ENABLE1_I2S0__WS_LSB				0
#define GPIO_IN_ENABLE1_I2S0__WS_MASK				0x000000ff
#define GPIO_IN_ENABLE1_I2S0__WS_GET(x)				(((x) & GPIO_IN_ENABLE1_I2S0__WS_MASK) >> GPIO_IN_ENABLE1_I2S0__WS_LSB)
#define GPIO_IN_ENABLE1_I2S0__WS_SET(x)				(((x) << GPIO_IN_ENABLE1_I2S0__WS_LSB) & GPIO_IN_ENABLE1_I2S0__WS_MASK)
#define GPIO_IN_ENABLE1_ADDRESS					0x18040048

// 0x1804004c	GPIO_IN_ENABLE2
#define GPIO_IN_ENABLE2_SLICEXT_MCLK_MSB			31
#define GPIO_IN_ENABLE2_SLICEXT_MCLK_LSB			24
#define GPIO_IN_ENABLE2_SLICEXT_MCLK_MASK			0xff000000
#define GPIO_IN_ENABLE2_SLICEXT_MCLK_GET(x)			(((x) & GPIO_IN_ENABLE2_SLICEXT_MCLK_MASK) >> GPIO_IN_ENABLE2_SLICEXT_MCLK_LSB)
#define GPIO_IN_ENABLE2_SLICEXT_MCLK_SET(x)			(((x) << GPIO_IN_ENABLE2_SLICEXT_MCLK_LSB) & GPIO_IN_ENABLE2_SLICEXT_MCLK_MASK)
#define GPIO_IN_ENABLE2_ETH__RX_CRS_MSB				23
#define GPIO_IN_ENABLE2_ETH__RX_CRS_LSB				16
#define GPIO_IN_ENABLE2_ETH__RX_CRS_MASK			0x00ff0000
#define GPIO_IN_ENABLE2_ETH__RX_CRS_GET(x)			(((x) & GPIO_IN_ENABLE2_ETH__RX_CRS_MASK) >> GPIO_IN_ENABLE2_ETH__RX_CRS_LSB)
#define GPIO_IN_ENABLE2_ETH__RX_CRS_SET(x)			(((x) << GPIO_IN_ENABLE2_ETH__RX_CRS_LSB) & GPIO_IN_ENABLE2_ETH__RX_CRS_MASK)
#define GPIO_IN_ENABLE2_ETH__RX_COL_MSB				15
#define GPIO_IN_ENABLE2_ETH__RX_COL_LSB				8
#define GPIO_IN_ENABLE2_ETH__RX_COL_MASK			0x0000ff00
#define GPIO_IN_ENABLE2_ETH__RX_COL_GET(x)			(((x) & GPIO_IN_ENABLE2_ETH__RX_COL_MASK) >> GPIO_IN_ENABLE2_ETH__RX_COL_LSB)
#define GPIO_IN_ENABLE2_ETH__RX_COL_SET(x)			(((x) << GPIO_IN_ENABLE2_ETH__RX_COL_LSB) & GPIO_IN_ENABLE2_ETH__RX_COL_MASK)
#define GPIO_IN_ENABLE2_ETH__RX_ERR_MSB				7
#define GPIO_IN_ENABLE2_ETH__RX_ERR_LSB				0
#define GPIO_IN_ENABLE2_ETH__RX_ERR_MASK			0x000000ff
#define GPIO_IN_ENABLE2_ETH__RX_ERR_GET(x)			(((x) & GPIO_IN_ENABLE2_ETH__RX_ERR_MASK) >> GPIO_IN_ENABLE2_ETH__RX_ERR_LSB)
#define GPIO_IN_ENABLE2_ETH__RX_ERR_SET(x)			(((x) << GPIO_IN_ENABLE2_ETH__RX_ERR_LSB) & GPIO_IN_ENABLE2_ETH__RX_ERR_MASK)
#define GPIO_IN_ENABLE2_ADDRESS					0x1804004c

// 0x18040050	GPIO_IN_ENABLE3
#define GPIO_IN_ENABLE3_MII_GE1_MDI_MSB				23
#define GPIO_IN_ENABLE3_MII_GE1_MDI_LSB				16
#define GPIO_IN_ENABLE3_MII_GE1_MDI_MASK			0x00ff0000
#define GPIO_IN_ENABLE3_MII_GE1_MDI_GET(x)			(((x) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK) >> GPIO_IN_ENABLE3_MII_GE1_MDI_LSB)
#define GPIO_IN_ENABLE3_MII_GE1_MDI_SET(x)			(((x) << GPIO_IN_ENABLE3_MII_GE1_MDI_LSB) & GPIO_IN_ENABLE3_MII_GE1_MDI_MASK)
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MSB			15
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB			8
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK			0x0000ff00
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_GET(x)			(((x) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK) >> GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB)
#define GPIO_IN_ENABLE3_BOOT_EXT_MDC_SET(x)			(((x) << GPIO_IN_ENABLE3_BOOT_EXT_MDC_LSB) & GPIO_IN_ENABLE3_BOOT_EXT_MDC_MASK)
#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_MSB			7
#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB			0
#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK			0x000000ff
#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_GET(x)			(((x) & GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK) >> GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB)
#define GPIO_IN_ENABLE3_BOOT_EXT_MDO_SET(x)			(((x) << GPIO_IN_ENABLE3_BOOT_EXT_MDO_LSB) & GPIO_IN_ENABLE3_BOOT_EXT_MDO_MASK)
#define GPIO_IN_ENABLE3_ADDRESS					0x18040050

// 0x18040054	GPIO_IN_ENABLE4
#define GPIO_IN_ENABLE4_I2C_DATA_MSB				31
#define GPIO_IN_ENABLE4_I2C_DATA_LSB				24
#define GPIO_IN_ENABLE4_I2C_DATA_MASK				0xff000000
#define GPIO_IN_ENABLE4_I2C_DATA_GET(x)				(((x) & GPIO_IN_ENABLE4_I2C_DATA_MASK) >> GPIO_IN_ENABLE4_I2C_DATA_LSB)
#define GPIO_IN_ENABLE4_I2C_DATA_SET(x)				(((x) << GPIO_IN_ENABLE4_I2C_DATA_LSB) & GPIO_IN_ENABLE4_I2C_DATA_MASK)
#define GPIO_IN_ENABLE4_I2C_CLK_MSB				23
#define GPIO_IN_ENABLE4_I2C_CLK_LSB				16
#define GPIO_IN_ENABLE4_I2C_CLK_MASK				0x00ff0000
#define GPIO_IN_ENABLE4_I2C_CLK_GET(x)				(((x) & GPIO_IN_ENABLE4_I2C_CLK_MASK) >> GPIO_IN_ENABLE4_I2C_CLK_LSB)
#define GPIO_IN_ENABLE4_I2C_CLK_SET(x)				(((x) << GPIO_IN_ENABLE4_I2C_CLK_LSB) & GPIO_IN_ENABLE4_I2C_CLK_MASK)
#define GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_MSB			15
#define GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_LSB			8
#define GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_MASK			0x0000ff00
#define GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_GET(x)			(((x) & GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_MASK) >> GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_LSB)
#define GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_SET(x)			(((x) << GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_LSB) & GPIO_IN_ENABLE4_SLIC_PCM_FS_IN_MASK)
#define GPIO_IN_ENABLE4_SLIC_DATA_IN_MSB			7
#define GPIO_IN_ENABLE4_SLIC_DATA_IN_LSB			0
#define GPIO_IN_ENABLE4_SLIC_DATA_IN_MASK			0x000000ff
#define GPIO_IN_ENABLE4_SLIC_DATA_IN_GET(x)			(((x) & GPIO_IN_ENABLE4_SLIC_DATA_IN_MASK) >> GPIO_IN_ENABLE4_SLIC_DATA_IN_LSB)
#define GPIO_IN_ENABLE4_SLIC_DATA_IN_SET(x)			(((x) << GPIO_IN_ENABLE4_SLIC_DATA_IN_LSB) & GPIO_IN_ENABLE4_SLIC_DATA_IN_MASK)
#define GPIO_IN_ENABLE4_ADDRESS					0x18040054

// 0x18040058	GPIO_IN_ENABLE5
#define GPIO_IN_ENABLE5_WMAC_IN3_MSB				31
#define GPIO_IN_ENABLE5_WMAC_IN3_LSB				24
#define GPIO_IN_ENABLE5_WMAC_IN3_MASK				0xff000000
#define GPIO_IN_ENABLE5_WMAC_IN3_GET(x)				(((x) & GPIO_IN_ENABLE5_WMAC_IN3_MASK) >> GPIO_IN_ENABLE5_WMAC_IN3_LSB)
#define GPIO_IN_ENABLE5_WMAC_IN3_SET(x)				(((x) << GPIO_IN_ENABLE5_WMAC_IN3_LSB) & GPIO_IN_ENABLE5_WMAC_IN3_MASK)
#define GPIO_IN_ENABLE5_WMAC_IN2_MSB				23
#define GPIO_IN_ENABLE5_WMAC_IN2_LSB				16
#define GPIO_IN_ENABLE5_WMAC_IN2_MASK				0x00ff0000
#define GPIO_IN_ENABLE5_WMAC_IN2_GET(x)				(((x) & GPIO_IN_ENABLE5_WMAC_IN2_MASK) >> GPIO_IN_ENABLE5_WMAC_IN2_LSB)
#define GPIO_IN_ENABLE5_WMAC_IN2_SET(x)				(((x) << GPIO_IN_ENABLE5_WMAC_IN2_LSB) & GPIO_IN_ENABLE5_WMAC_IN2_MASK)
#define GPIO_IN_ENABLE5_WMAC_IN1_MSB				15
#define GPIO_IN_ENABLE5_WMAC_IN1_LSB				8
#define GPIO_IN_ENABLE5_WMAC_IN1_MASK				0x0000ff00
#define GPIO_IN_ENABLE5_WMAC_IN1_GET(x)				(((x) & GPIO_IN_ENABLE5_WMAC_IN1_MASK) >> GPIO_IN_ENABLE5_WMAC_IN1_LSB)
#define GPIO_IN_ENABLE5_WMAC_IN1_SET(x)				(((x) << GPIO_IN_ENABLE5_WMAC_IN1_LSB) & GPIO_IN_ENABLE5_WMAC_IN1_MASK)
#define GPIO_IN_ENABLE5_WMAC_IN0_MSB				7
#define GPIO_IN_ENABLE5_WMAC_IN0_LSB				0
#define GPIO_IN_ENABLE5_WMAC_IN0_MASK				0x000000ff
#define GPIO_IN_ENABLE5_WMAC_IN0_GET(x)				(((x) & GPIO_IN_ENABLE5_WMAC_IN0_MASK) >> GPIO_IN_ENABLE5_WMAC_IN0_LSB)
#define GPIO_IN_ENABLE5_WMAC_IN0_SET(x)				(((x) << GPIO_IN_ENABLE5_WMAC_IN0_LSB) & GPIO_IN_ENABLE5_WMAC_IN0_MASK)
#define GPIO_IN_ENABLE5_ADDRESS					0x18040058

// 0x1804005c	GPIO_IN_ENABLE6
#define GPIO_IN_ENABLE6_WMAC_IN7_MSB				31
#define GPIO_IN_ENABLE6_WMAC_IN7_LSB				24
#define GPIO_IN_ENABLE6_WMAC_IN7_MASK				0xff000000
#define GPIO_IN_ENABLE6_WMAC_IN7_GET(x)				(((x) & GPIO_IN_ENABLE6_WMAC_IN7_MASK) >> GPIO_IN_ENABLE6_WMAC_IN7_LSB)
#define GPIO_IN_ENABLE6_WMAC_IN7_SET(x)				(((x) << GPIO_IN_ENABLE6_WMAC_IN7_LSB) & GPIO_IN_ENABLE6_WMAC_IN7_MASK)
#define GPIO_IN_ENABLE6_WMAC_IN6_MSB				23
#define GPIO_IN_ENABLE6_WMAC_IN6_LSB				16
#define GPIO_IN_ENABLE6_WMAC_IN6_MASK				0x00ff0000
#define GPIO_IN_ENABLE6_WMAC_IN6_GET(x)				(((x) & GPIO_IN_ENABLE6_WMAC_IN6_MASK) >> GPIO_IN_ENABLE6_WMAC_IN6_LSB)
#define GPIO_IN_ENABLE6_WMAC_IN6_SET(x)				(((x) << GPIO_IN_ENABLE6_WMAC_IN6_LSB) & GPIO_IN_ENABLE6_WMAC_IN6_MASK)
#define GPIO_IN_ENABLE6_WMAC_IN5_MSB				15
#define GPIO_IN_ENABLE6_WMAC_IN5_LSB				8
#define GPIO_IN_ENABLE6_WMAC_IN5_MASK				0x0000ff00
#define GPIO_IN_ENABLE6_WMAC_IN5_GET(x)				(((x) & GPIO_IN_ENABLE6_WMAC_IN5_MASK) >> GPIO_IN_ENABLE6_WMAC_IN5_LSB)
#define GPIO_IN_ENABLE6_WMAC_IN5_SET(x)				(((x) << GPIO_IN_ENABLE6_WMAC_IN5_LSB) & GPIO_IN_ENABLE6_WMAC_IN5_MASK)
#define GPIO_IN_ENABLE6_WMAC_IN4_MSB				7
#define GPIO_IN_ENABLE6_WMAC_IN4_LSB				0
#define GPIO_IN_ENABLE6_WMAC_IN4_MASK				0x000000ff
#define GPIO_IN_ENABLE6_WMAC_IN4_GET(x)				(((x) & GPIO_IN_ENABLE6_WMAC_IN4_MASK) >> GPIO_IN_ENABLE6_WMAC_IN4_LSB)
#define GPIO_IN_ENABLE6_WMAC_IN4_SET(x)				(((x) << GPIO_IN_ENABLE6_WMAC_IN4_LSB) & GPIO_IN_ENABLE6_WMAC_IN4_MASK)
#define GPIO_IN_ENABLE6_ADDRESS					0x1804005c

// 0x18040060	GPIO_IN_ENABLE7
#define GPIO_IN_ENABLE7_WMAC_IN11_MSB				31
#define GPIO_IN_ENABLE7_WMAC_IN11_LSB				24
#define GPIO_IN_ENABLE7_WMAC_IN11_MASK				0xff000000
#define GPIO_IN_ENABLE7_WMAC_IN11_GET(x)			(((x) & GPIO_IN_ENABLE7_WMAC_IN11_MASK) >> GPIO_IN_ENABLE7_WMAC_IN11_LSB)
#define GPIO_IN_ENABLE7_WMAC_IN11_SET(x)			(((x) << GPIO_IN_ENABLE7_WMAC_IN11_LSB) & GPIO_IN_ENABLE7_WMAC_IN11_MASK)
#define GPIO_IN_ENABLE7_WMAC_IN10_MSB				23
#define GPIO_IN_ENABLE7_WMAC_IN10_LSB				16
#define GPIO_IN_ENABLE7_WMAC_IN10_MASK				0x00ff0000
#define GPIO_IN_ENABLE7_WMAC_IN10_GET(x)			(((x) & GPIO_IN_ENABLE7_WMAC_IN10_MASK) >> GPIO_IN_ENABLE7_WMAC_IN10_LSB)
#define GPIO_IN_ENABLE7_WMAC_IN10_SET(x)			(((x) << GPIO_IN_ENABLE7_WMAC_IN10_LSB) & GPIO_IN_ENABLE7_WMAC_IN10_MASK)
#define GPIO_IN_ENABLE7_WMAC_IN9_MSB				15
#define GPIO_IN_ENABLE7_WMAC_IN9_LSB				8
#define GPIO_IN_ENABLE7_WMAC_IN9_MASK				0x0000ff00
#define GPIO_IN_ENABLE7_WMAC_IN9_GET(x)				(((x) & GPIO_IN_ENABLE7_WMAC_IN9_MASK) >> GPIO_IN_ENABLE7_WMAC_IN9_LSB)
#define GPIO_IN_ENABLE7_WMAC_IN9_SET(x)				(((x) << GPIO_IN_ENABLE7_WMAC_IN9_LSB) & GPIO_IN_ENABLE7_WMAC_IN9_MASK)
#define GPIO_IN_ENABLE7_WMAC_IN8_MSB				7
#define GPIO_IN_ENABLE7_WMAC_IN8_LSB				0
#define GPIO_IN_ENABLE7_WMAC_IN8_MASK				0x000000ff
#define GPIO_IN_ENABLE7_WMAC_IN8_GET(x)				(((x) & GPIO_IN_ENABLE7_WMAC_IN8_MASK) >> GPIO_IN_ENABLE7_WMAC_IN8_LSB)
#define GPIO_IN_ENABLE7_WMAC_IN8_SET(x)				(((x) << GPIO_IN_ENABLE7_WMAC_IN8_LSB) & GPIO_IN_ENABLE7_WMAC_IN8_MASK)
#define GPIO_IN_ENABLE7_ADDRESS					0x18040060

// 0x18040064	GPIO_IN_ENABLE8
#define GPIO_IN_ENABLE8_SRIF_SRESET_MSB				31
#define GPIO_IN_ENABLE8_SRIF_SRESET_LSB				24
#define GPIO_IN_ENABLE8_SRIF_SRESET_MASK			0xff000000
#define GPIO_IN_ENABLE8_SRIF_SRESET_GET(x)			(((x) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK) >> GPIO_IN_ENABLE8_SRIF_SRESET_LSB)
#define GPIO_IN_ENABLE8_SRIF_SRESET_SET(x)			(((x) << GPIO_IN_ENABLE8_SRIF_SRESET_LSB) & GPIO_IN_ENABLE8_SRIF_SRESET_MASK)
#define GPIO_IN_ENABLE8_SRIF_SIN_MSB				23
#define GPIO_IN_ENABLE8_SRIF_SIN_LSB				16
#define GPIO_IN_ENABLE8_SRIF_SIN_MASK				0x00ff0000
#define GPIO_IN_ENABLE8_SRIF_SIN_GET(x)				(((x) & GPIO_IN_ENABLE8_SRIF_SIN_MASK) >> GPIO_IN_ENABLE8_SRIF_SIN_LSB)
#define GPIO_IN_ENABLE8_SRIF_SIN_SET(x)				(((x) << GPIO_IN_ENABLE8_SRIF_SIN_LSB) & GPIO_IN_ENABLE8_SRIF_SIN_MASK)
#define GPIO_IN_ENABLE8_SRIF_SOT_MSB				15
#define GPIO_IN_ENABLE8_SRIF_SOT_LSB				8
#define GPIO_IN_ENABLE8_SRIF_SOT_MASK				0x0000ff00
#define GPIO_IN_ENABLE8_SRIF_SOT_GET(x)				(((x) & GPIO_IN_ENABLE8_SRIF_SOT_MASK) >> GPIO_IN_ENABLE8_SRIF_SOT_LSB)
#define GPIO_IN_ENABLE8_SRIF_SOT_SET(x)				(((x) << GPIO_IN_ENABLE8_SRIF_SOT_LSB) & GPIO_IN_ENABLE8_SRIF_SOT_MASK)
#define GPIO_IN_ENABLE8_SRIF_SCLK_MSB				7
#define GPIO_IN_ENABLE8_SRIF_SCLK_LSB				0
#define GPIO_IN_ENABLE8_SRIF_SCLK_MASK				0x000000ff
#define GPIO_IN_ENABLE8_SRIF_SCLK_GET(x)			(((x) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK) >> GPIO_IN_ENABLE8_SRIF_SCLK_LSB)
#define GPIO_IN_ENABLE8_SRIF_SCLK_SET(x)			(((x) << GPIO_IN_ENABLE8_SRIF_SCLK_LSB) & GPIO_IN_ENABLE8_SRIF_SCLK_MASK)
#define GPIO_IN_ENABLE8_ADDRESS					0x18040064

// 0x18040068	GPIO_IN_ENABLE9
#define GPIO_IN_ENABLE9_UART1_CTS_MSB				31
#define GPIO_IN_ENABLE9_UART1_CTS_LSB				24
#define GPIO_IN_ENABLE9_UART1_CTS_MASK				0xff000000
#define GPIO_IN_ENABLE9_UART1_CTS_GET(x)			(((x) & GPIO_IN_ENABLE9_UART1_CTS_MASK) >> GPIO_IN_ENABLE9_UART1_CTS_LSB)
#define GPIO_IN_ENABLE9_UART1_CTS_SET(x)			(((x) << GPIO_IN_ENABLE9_UART1_CTS_LSB) & GPIO_IN_ENABLE9_UART1_CTS_MASK)
#define GPIO_IN_ENABLE9_UART1_RD_MSB				23
#define GPIO_IN_ENABLE9_UART1_RD_LSB				16
#define GPIO_IN_ENABLE9_UART1_RD_MASK				0x00ff0000
#define GPIO_IN_ENABLE9_UART1_RD_GET(x)				(((x) & GPIO_IN_ENABLE9_UART1_RD_MASK) >> GPIO_IN_ENABLE9_UART1_RD_LSB)
#define GPIO_IN_ENABLE9_UART1_RD_SET(x)				(((x) << GPIO_IN_ENABLE9_UART1_RD_LSB) & GPIO_IN_ENABLE9_UART1_RD_MASK)
#define GPIO_IN_ENABLE9_UART1_RTS_MSB				15
#define GPIO_IN_ENABLE9_UART1_RTS_LSB				8
#define GPIO_IN_ENABLE9_UART1_RTS_MASK				0x0000ff00
#define GPIO_IN_ENABLE9_UART1_RTS_GET(x)			(((x) & GPIO_IN_ENABLE9_UART1_RTS_MASK) >> GPIO_IN_ENABLE9_UART1_RTS_LSB)
#define GPIO_IN_ENABLE9_UART1_RTS_SET(x)			(((x) << GPIO_IN_ENABLE9_UART1_RTS_LSB) & GPIO_IN_ENABLE9_UART1_RTS_MASK)
#define GPIO_IN_ENABLE9_UART1_TD_MSB				7
#define GPIO_IN_ENABLE9_UART1_TD_LSB				0
#define GPIO_IN_ENABLE9_UART1_TD_MASK				0x000000ff
#define GPIO_IN_ENABLE9_UART1_TD_GET(x)				(((x) & GPIO_IN_ENABLE9_UART1_TD_MASK) >> GPIO_IN_ENABLE9_UART1_TD_LSB)
#define GPIO_IN_ENABLE9_UART1_TD_SET(x)				(((x) << GPIO_IN_ENABLE9_UART1_TD_LSB) & GPIO_IN_ENABLE9_UART1_TD_MASK)
#define GPIO_IN_ENABLE9_ADDRESS					0x18040068

// 0x1804006c	GPIO_FUNCTION
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MSB			11
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB			11
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK			0x00000800
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS9_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS9_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS9_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MSB			10
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB			10
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK			0x00000400
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS8_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS8_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS8_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MSB			9
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB			9
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK			0x00000200
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS7_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS7_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS7_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MSB			8
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB			8
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK			0x00000100
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS6_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS6_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS6_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MSB			7
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB			7
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK			0x00000080
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS5_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS5_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS5_ENABLE_RESET			0x1 // 1
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MSB			6
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB			6
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK			0x00000040
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS4_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS4_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS4_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MSB			5
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB			5
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK			0x00000020
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS3_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS3_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS3_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MSB			4
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB			4
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK			0x00000010
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS2_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS2_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS2_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MSB			3
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB			3
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK			0x00000008
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS1_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS1_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS1_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MSB			2
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB			2
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK			0x00000004
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_GET(x)			(((x) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK) >> GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB)
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_SET(x)			(((x) << GPIO_FUNCTION_CLK_OBS0_ENABLE_LSB) & GPIO_FUNCTION_CLK_OBS0_ENABLE_MASK)
#define GPIO_FUNCTION_CLK_OBS0_ENABLE_RESET			0x0 // 0
#define GPIO_FUNCTION_DISABLE_JTAG_MSB				1
#define GPIO_FUNCTION_DISABLE_JTAG_LSB				1
#define GPIO_FUNCTION_DISABLE_JTAG_MASK				0x00000002
#define GPIO_FUNCTION_DISABLE_JTAG_GET(x)			(((x) & GPIO_FUNCTION_DISABLE_JTAG_MASK) >> GPIO_FUNCTION_DISABLE_JTAG_LSB)
#define GPIO_FUNCTION_DISABLE_JTAG_SET(x)			(((x) << GPIO_FUNCTION_DISABLE_JTAG_LSB) & GPIO_FUNCTION_DISABLE_JTAG_MASK)
#define GPIO_FUNCTION_DISABLE_JTAG_RESET			0x0 // 0
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MSB			0
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB			0
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK			0x00000001
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_GET(x)			(((x) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK) >> GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB)
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_SET(x)			(((x) << GPIO_FUNCTION_ENABLE_GPIO_SRIF_LSB) & GPIO_FUNCTION_ENABLE_GPIO_SRIF_MASK)
#define GPIO_FUNCTION_ENABLE_GPIO_SRIF_RESET			0x0 // 0
#define GPIO_FUNCTION_ADDRESS					0x1804006c

// 0x18050000	CPU_PLL_CONFIG
#define CPU_PLL_CONFIG_UPDATING_MSB				31
#define CPU_PLL_CONFIG_UPDATING_LSB				31
#define CPU_PLL_CONFIG_UPDATING_MASK				0x80000000
#define CPU_PLL_CONFIG_UPDATING_GET(x)				(((x) & CPU_PLL_CONFIG_UPDATING_MASK) >> CPU_PLL_CONFIG_UPDATING_LSB)
#define CPU_PLL_CONFIG_UPDATING_SET(x)				(((x) << CPU_PLL_CONFIG_UPDATING_LSB) & CPU_PLL_CONFIG_UPDATING_MASK)
#define CPU_PLL_CONFIG_UPDATING_RESET				0x1 // 1
#define CPU_PLL_CONFIG_PLLPWD_MSB				30
#define CPU_PLL_CONFIG_PLLPWD_LSB				30
#define CPU_PLL_CONFIG_PLLPWD_MASK				0x40000000
#define CPU_PLL_CONFIG_PLLPWD_GET(x)				(((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
#define CPU_PLL_CONFIG_PLLPWD_SET(x)				(((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
#define CPU_PLL_CONFIG_PLLPWD_RESET				0x1 // 1
#define CPU_PLL_CONFIG_SPARE_MSB				29
#define CPU_PLL_CONFIG_SPARE_LSB				22
#define CPU_PLL_CONFIG_SPARE_MASK				0x3fc00000
#define CPU_PLL_CONFIG_SPARE_GET(x)				(((x) & CPU_PLL_CONFIG_SPARE_MASK) >> CPU_PLL_CONFIG_SPARE_LSB)
#define CPU_PLL_CONFIG_SPARE_SET(x)				(((x) << CPU_PLL_CONFIG_SPARE_LSB) & CPU_PLL_CONFIG_SPARE_MASK)
#define CPU_PLL_CONFIG_SPARE_RESET				0x0 // 0
#define CPU_PLL_CONFIG_OUTDIV_MSB				21
#define CPU_PLL_CONFIG_OUTDIV_LSB				19
#define CPU_PLL_CONFIG_OUTDIV_MASK				0x00380000
#define CPU_PLL_CONFIG_OUTDIV_GET(x)				(((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
#define CPU_PLL_CONFIG_OUTDIV_SET(x)				(((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
#define CPU_PLL_CONFIG_OUTDIV_RESET				0x0 // 0
#define CPU_PLL_CONFIG_RANGE_MSB				18
#define CPU_PLL_CONFIG_RANGE_LSB				17
#define CPU_PLL_CONFIG_RANGE_MASK				0x00060000
#define CPU_PLL_CONFIG_RANGE_GET(x)				(((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
#define CPU_PLL_CONFIG_RANGE_SET(x)				(((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
#define CPU_PLL_CONFIG_RANGE_RESET				0x3 // 3
#define CPU_PLL_CONFIG_REFDIV_MSB				16
#define CPU_PLL_CONFIG_REFDIV_LSB				12
#define CPU_PLL_CONFIG_REFDIV_MASK				0x0001f000
#define CPU_PLL_CONFIG_REFDIV_GET(x)				(((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
#define CPU_PLL_CONFIG_REFDIV_SET(x)				(((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
#define CPU_PLL_CONFIG_REFDIV_RESET				0x2 // 2
#define CPU_PLL_CONFIG_NINT_MSB					11
#define CPU_PLL_CONFIG_NINT_LSB					6
#define CPU_PLL_CONFIG_NINT_MASK				0x00000fc0
#define CPU_PLL_CONFIG_NINT_GET(x)				(((x) & CPU_PLL_CONFIG_NINT_MASK) >> CPU_PLL_CONFIG_NINT_LSB)
#define CPU_PLL_CONFIG_NINT_SET(x)				(((x) << CPU_PLL_CONFIG_NINT_LSB) & CPU_PLL_CONFIG_NINT_MASK)
#define CPU_PLL_CONFIG_NFRAC_MSB				5
#define CPU_PLL_CONFIG_NFRAC_LSB				0
#define CPU_PLL_CONFIG_NFRAC_MASK				0x0000003f
#define CPU_PLL_CONFIG_NFRAC_GET(x)				(((x) & CPU_PLL_CONFIG_NFRAC_MASK) >> CPU_PLL_CONFIG_NFRAC_LSB)
#define CPU_PLL_CONFIG_NFRAC_SET(x)				(((x) << CPU_PLL_CONFIG_NFRAC_LSB) & CPU_PLL_CONFIG_NFRAC_MASK)
#define CPU_PLL_CONFIG_ADDRESS					0x18050000

// 0x18050004	DDR_PLL_CONFIG
#define DDR_PLL_CONFIG_UPDATING_MSB				31
#define DDR_PLL_CONFIG_UPDATING_LSB				31
#define DDR_PLL_CONFIG_UPDATING_MASK				0x80000000
#define DDR_PLL_CONFIG_UPDATING_GET(x)				(((x) & DDR_PLL_CONFIG_UPDATING_MASK) >> DDR_PLL_CONFIG_UPDATING_LSB)
#define DDR_PLL_CONFIG_UPDATING_SET(x)				(((x) << DDR_PLL_CONFIG_UPDATING_LSB) & DDR_PLL_CONFIG_UPDATING_MASK)
#define DDR_PLL_CONFIG_UPDATING_RESET				0x1 // 1
#define DDR_PLL_CONFIG_PLLPWD_MSB				30
#define DDR_PLL_CONFIG_PLLPWD_LSB				30
#define DDR_PLL_CONFIG_PLLPWD_MASK				0x40000000
#define DDR_PLL_CONFIG_PLLPWD_GET(x)				(((x) & DDR_PLL_CONFIG_PLLPWD_MASK) >> DDR_PLL_CONFIG_PLLPWD_LSB)
#define DDR_PLL_CONFIG_PLLPWD_SET(x)				(((x) << DDR_PLL_CONFIG_PLLPWD_LSB) & DDR_PLL_CONFIG_PLLPWD_MASK)
#define DDR_PLL_CONFIG_PLLPWD_RESET				0x1 // 1
#define DDR_PLL_CONFIG_SPARE_MSB				29
#define DDR_PLL_CONFIG_SPARE_LSB				26
#define DDR_PLL_CONFIG_SPARE_MASK				0x3c000000
#define DDR_PLL_CONFIG_SPARE_GET(x)				(((x) & DDR_PLL_CONFIG_SPARE_MASK) >> DDR_PLL_CONFIG_SPARE_LSB)
#define DDR_PLL_CONFIG_SPARE_SET(x)				(((x) << DDR_PLL_CONFIG_SPARE_LSB) & DDR_PLL_CONFIG_SPARE_MASK)
#define DDR_PLL_CONFIG_SPARE_RESET				0x0 // 0
#define DDR_PLL_CONFIG_OUTDIV_MSB				25
#define DDR_PLL_CONFIG_OUTDIV_LSB				23
#define DDR_PLL_CONFIG_OUTDIV_MASK				0x03800000
#define DDR_PLL_CONFIG_OUTDIV_GET(x)				(((x) & DDR_PLL_CONFIG_OUTDIV_MASK) >> DDR_PLL_CONFIG_OUTDIV_LSB)
#define DDR_PLL_CONFIG_OUTDIV_SET(x)				(((x) << DDR_PLL_CONFIG_OUTDIV_LSB) & DDR_PLL_CONFIG_OUTDIV_MASK)
#define DDR_PLL_CONFIG_OUTDIV_RESET				0x0 // 0
#define DDR_PLL_CONFIG_RANGE_MSB				22
#define DDR_PLL_CONFIG_RANGE_LSB				21
#define DDR_PLL_CONFIG_RANGE_MASK				0x00600000
#define DDR_PLL_CONFIG_RANGE_GET(x)				(((x) & DDR_PLL_CONFIG_RANGE_MASK) >> DDR_PLL_CONFIG_RANGE_LSB)
#define DDR_PLL_CONFIG_RANGE_SET(x)				(((x) << DDR_PLL_CONFIG_RANGE_LSB) & DDR_PLL_CONFIG_RANGE_MASK)
#define DDR_PLL_CONFIG_RANGE_RESET				0x3 // 3
#define DDR_PLL_CONFIG_REFDIV_MSB				20
#define DDR_PLL_CONFIG_REFDIV_LSB				16
#define DDR_PLL_CONFIG_REFDIV_MASK				0x001f0000
#define DDR_PLL_CONFIG_REFDIV_GET(x)				(((x) & DDR_PLL_CONFIG_REFDIV_MASK) >> DDR_PLL_CONFIG_REFDIV_LSB)
#define DDR_PLL_CONFIG_REFDIV_SET(x)				(((x) << DDR_PLL_CONFIG_REFDIV_LSB) & DDR_PLL_CONFIG_REFDIV_MASK)
#define DDR_PLL_CONFIG_REFDIV_RESET				0x2 // 2
#define DDR_PLL_CONFIG_NINT_MSB					15
#define DDR_PLL_CONFIG_NINT_LSB					10
#define DDR_PLL_CONFIG_NINT_MASK				0x0000fc00
#define DDR_PLL_CONFIG_NINT_GET(x)				(((x) & DDR_PLL_CONFIG_NINT_MASK) >> DDR_PLL_CONFIG_NINT_LSB)
#define DDR_PLL_CONFIG_NINT_SET(x)				(((x) << DDR_PLL_CONFIG_NINT_LSB) & DDR_PLL_CONFIG_NINT_MASK)
#define DDR_PLL_CONFIG_NFRAC_MSB				9
#define DDR_PLL_CONFIG_NFRAC_LSB				0
#define DDR_PLL_CONFIG_NFRAC_MASK				0x000003ff
#define DDR_PLL_CONFIG_NFRAC_GET(x)				(((x) & DDR_PLL_CONFIG_NFRAC_MASK) >> DDR_PLL_CONFIG_NFRAC_LSB)
#define DDR_PLL_CONFIG_NFRAC_SET(x)				(((x) << DDR_PLL_CONFIG_NFRAC_LSB) & DDR_PLL_CONFIG_NFRAC_MASK)
#define DDR_PLL_CONFIG_ADDRESS					0x18050004

// 0x18050008	CPU_DDR_CLOCK_CONTROL
#define CPU_DDR_CLOCK_CONTROL_SPARE_MSB				31
#define CPU_DDR_CLOCK_CONTROL_SPARE_LSB				25
#define CPU_DDR_CLOCK_CONTROL_SPARE_MASK			0xfe000000
#define CPU_DDR_CLOCK_CONTROL_SPARE_GET(x)			(((x) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK) >> CPU_DDR_CLOCK_CONTROL_SPARE_LSB)
#define CPU_DDR_CLOCK_CONTROL_SPARE_SET(x)			(((x) << CPU_DDR_CLOCK_CONTROL_SPARE_LSB) & CPU_DDR_CLOCK_CONTROL_SPARE_MASK)
#define CPU_DDR_CLOCK_CONTROL_SPARE_RESET			0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MSB		24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB		24
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK		0x01000000
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHBCLK_FROM_DDRPLL_RESET		0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MSB	23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB	23
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK	0x00800000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_GET(x)	(((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_SET(x)	(((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_DEASSRT_RESET	0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MSB		22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB		22
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK		0x00400000
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_GET(x)	(((x) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_SET(x)	(((x) << CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_RESET_EN_BP_ASRT_RESET	0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MSB	21
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB	21
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK	0x00200000
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_GET(x)	(((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_SET(x)	(((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_CPUPLL_RESET	0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MSB	20
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB	20
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK	0x00100000
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_GET(x)	(((x) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_SET(x)	(((x) << CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_DDR_CLK_FROM_DDRPLL_RESET	0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MSB			19
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB			15
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK			0x000f8000
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_RESET		0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MSB			14
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB			10
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK			0x00007c00
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_RESET		0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MSB			9
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB			5
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK			0x000003e0
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_RESET		0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MSB		4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB		4
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK		0x00000010
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_RESET		0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MSB		3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB		3
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK		0x00000008
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_DDR_PLL_BYPASS_RESET		0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MSB		2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB		2
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK		0x00000004
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK) >> CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_LSB) & CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_MASK)
#define CPU_DDR_CLOCK_CONTROL_CPU_PLL_BYPASS_RESET		0x1 // 1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MSB			1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB			1
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK			0x00000002
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_RESET_SWITCH_RESET		0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MSB			0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB			0
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK			0x00000001
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_GET(x)		(((x) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK) >> CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_SET(x)		(((x) << CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_LSB) & CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_MASK)
#define CPU_DDR_CLOCK_CONTROL_CLOCK_SWITCH_RESET		0x0 // 0
#define CPU_DDR_CLOCK_CONTROL_ADDRESS				0x18050008

// 0x1805000c	PCIE_PLL_CONFIG
#define PCIE_PLL_CONFIG_UPDATING_MSB				31
#define PCIE_PLL_CONFIG_UPDATING_LSB				31
#define PCIE_PLL_CONFIG_UPDATING_MASK				0x80000000
#define PCIE_PLL_CONFIG_UPDATING_GET(x)				(((x) & PCIE_PLL_CONFIG_UPDATING_MASK) >> PCIE_PLL_CONFIG_UPDATING_LSB)
#define PCIE_PLL_CONFIG_UPDATING_SET(x)				(((x) << PCIE_PLL_CONFIG_UPDATING_LSB) & PCIE_PLL_CONFIG_UPDATING_MASK)
#define PCIE_PLL_CONFIG_UPDATING_RESET				0x0 // 0
#define PCIE_PLL_CONFIG_PLLPWD_MSB				30
#define PCIE_PLL_CONFIG_PLLPWD_LSB				30
#define PCIE_PLL_CONFIG_PLLPWD_MASK				0x40000000
#define PCIE_PLL_CONFIG_PLLPWD_GET(x)				(((x) & PCIE_PLL_CONFIG_PLLPWD_MASK) >> PCIE_PLL_CONFIG_PLLPWD_LSB)
#define PCIE_PLL_CONFIG_PLLPWD_SET(x)				(((x) << PCIE_PLL_CONFIG_PLLPWD_LSB) & PCIE_PLL_CONFIG_PLLPWD_MASK)
#define PCIE_PLL_CONFIG_PLLPWD_RESET				0x1 // 1
#define PCIE_PLL_CONFIG_BYPASS_MSB				16
#define PCIE_PLL_CONFIG_BYPASS_LSB				16
#define PCIE_PLL_CONFIG_BYPASS_MASK				0x00010000
#define PCIE_PLL_CONFIG_BYPASS_GET(x)				(((x) & PCIE_PLL_CONFIG_BYPASS_MASK) >> PCIE_PLL_CONFIG_BYPASS_LSB)
#define PCIE_PLL_CONFIG_BYPASS_SET(x)				(((x) << PCIE_PLL_CONFIG_BYPASS_LSB) & PCIE_PLL_CONFIG_BYPASS_MASK)
#define PCIE_PLL_CONFIG_BYPASS_RESET				0x1 // 1
#define PCIE_PLL_CONFIG_REFDIV_MSB				14
#define PCIE_PLL_CONFIG_REFDIV_LSB				10
#define PCIE_PLL_CONFIG_REFDIV_MASK				0x00007c00
#define PCIE_PLL_CONFIG_REFDIV_GET(x)				(((x) & PCIE_PLL_CONFIG_REFDIV_MASK) >> PCIE_PLL_CONFIG_REFDIV_LSB)
#define PCIE_PLL_CONFIG_REFDIV_SET(x)				(((x) << PCIE_PLL_CONFIG_REFDIV_LSB) & PCIE_PLL_CONFIG_REFDIV_MASK)
#define PCIE_PLL_CONFIG_REFDIV_RESET				0x1 // 1
#define PCIE_PLL_CONFIG_ADDRESS					0x1805000c

// 0x18050010	PCIE_PLL_DITHER_DIV_MAX
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MSB			31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB			31
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK			0x80000000
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_GET(x)		(((x) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK) >> PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(x)		(((x) << PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_LSB) & PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_RESET			0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MSB			30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB			30
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK			0x40000000
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_GET(x)			(((x) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK) >> PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(x)			(((x) << PCIE_PLL_DITHER_DIV_MAX_USE_MAX_LSB) & PCIE_PLL_DITHER_DIV_MAX_USE_MAX_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_USE_MAX_RESET			0x1 // 1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MSB			20
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB			15
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK		0x001f8000
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_GET(x)		(((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(x)		(((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MSB		14
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB		1
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK		0x00007ffe
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_GET(x)		(((x) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(x)		(((x) << PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MAX_ADDRESS				0x18050010

// 0x18050014	PCIE_PLL_DITHER_DIV_MIN
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MSB			20
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB			15
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK		0x001f8000
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_GET(x)		(((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(x)		(((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MSB		14
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB		1
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK		0x00007ffe
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_GET(x)		(((x) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK) >> PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB)
#define PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(x)		(((x) << PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_LSB) & PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_MASK)
#define PCIE_PLL_DITHER_DIV_MIN_ADDRESS				0x18050014

// 0x18050018	PCIE_PLL_DITHER_STEP
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MSB			31
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB			28
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK			0xf0000000
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_GET(x)			(((x) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK) >> PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_SET(x)			(((x) << PCIE_PLL_DITHER_STEP_UPDATE_CNT_LSB) & PCIE_PLL_DITHER_STEP_UPDATE_CNT_MASK)
#define PCIE_PLL_DITHER_STEP_UPDATE_CNT_RESET			0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_INT_MSB			24
#define PCIE_PLL_DITHER_STEP_STEP_INT_LSB			15
#define PCIE_PLL_DITHER_STEP_STEP_INT_MASK			0x01ff8000
#define PCIE_PLL_DITHER_STEP_STEP_INT_GET(x)			(((x) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK) >> PCIE_PLL_DITHER_STEP_STEP_INT_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_INT_SET(x)			(((x) << PCIE_PLL_DITHER_STEP_STEP_INT_LSB) & PCIE_PLL_DITHER_STEP_STEP_INT_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_INT_RESET			0x0 // 0
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MSB			14
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB			1
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK			0x00007ffe
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_GET(x)			(((x) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK) >> PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_SET(x)			(((x) << PCIE_PLL_DITHER_STEP_STEP_FRAC_LSB) & PCIE_PLL_DITHER_STEP_STEP_FRAC_MASK)
#define PCIE_PLL_DITHER_STEP_STEP_FRAC_RESET			0xa // 10
#define PCIE_PLL_DITHER_STEP_ADDRESS				0x18050018

// 0x1805001c	LDO_POWER_CONTROL
#define LDO_POWER_CONTROL_PKG_SEL_MSB				5
#define LDO_POWER_CONTROL_PKG_SEL_LSB				5
#define LDO_POWER_CONTROL_PKG_SEL_MASK				0x00000020
#define LDO_POWER_CONTROL_PKG_SEL_GET(x)			(((x) & LDO_POWER_CONTROL_PKG_SEL_MASK) >> LDO_POWER_CONTROL_PKG_SEL_LSB)
#define LDO_POWER_CONTROL_PKG_SEL_SET(x)			(((x) << LDO_POWER_CONTROL_PKG_SEL_LSB) & LDO_POWER_CONTROL_PKG_SEL_MASK)
#define LDO_POWER_CONTROL_PKG_SEL_RESET				0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_CPU_MSB			4
#define LDO_POWER_CONTROL_PWDLDO_CPU_LSB			4
#define LDO_POWER_CONTROL_PWDLDO_CPU_MASK			0x00000010
#define LDO_POWER_CONTROL_PWDLDO_CPU_GET(x)			(((x) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK) >> LDO_POWER_CONTROL_PWDLDO_CPU_LSB)
#define LDO_POWER_CONTROL_PWDLDO_CPU_SET(x)			(((x) << LDO_POWER_CONTROL_PWDLDO_CPU_LSB) & LDO_POWER_CONTROL_PWDLDO_CPU_MASK)
#define LDO_POWER_CONTROL_PWDLDO_CPU_RESET			0x0 // 0
#define LDO_POWER_CONTROL_PWDLDO_DDR_MSB			3
#define LDO_POWER_CONTROL_PWDLDO_DDR_LSB			3
#define LDO_POWER_CONTROL_PWDLDO_DDR_MASK			0x00000008
#define LDO_POWER_CONTROL_PWDLDO_DDR_GET(x)			(((x) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK) >> LDO_POWER_CONTROL_PWDLDO_DDR_LSB)
#define LDO_POWER_CONTROL_PWDLDO_DDR_SET(x)			(((x) << LDO_POWER_CONTROL_PWDLDO_DDR_LSB) & LDO_POWER_CONTROL_PWDLDO_DDR_MASK)
#define LDO_POWER_CONTROL_PWDLDO_DDR_RESET			0x0 // 0
#define LDO_POWER_CONTROL_CPU_REFSEL_MSB			2
#define LDO_POWER_CONTROL_CPU_REFSEL_LSB			1
#define LDO_POWER_CONTROL_CPU_REFSEL_MASK			0x00000006
#define LDO_POWER_CONTROL_CPU_REFSEL_GET(x)			(((x) & LDO_POWER_CONTROL_CPU_REFSEL_MASK) >> LDO_POWER_CONTROL_CPU_REFSEL_LSB)
#define LDO_POWER_CONTROL_CPU_REFSEL_SET(x)			(((x) << LDO_POWER_CONTROL_CPU_REFSEL_LSB) & LDO_POWER_CONTROL_CPU_REFSEL_MASK)
#define LDO_POWER_CONTROL_CPU_REFSEL_RESET			0x3 // 3
#define LDO_POWER_CONTROL_SELECT_DDR1_MSB			0
#define LDO_POWER_CONTROL_SELECT_DDR1_LSB			0
#define LDO_POWER_CONTROL_SELECT_DDR1_MASK			0x00000001
#define LDO_POWER_CONTROL_SELECT_DDR1_GET(x)			(((x) & LDO_POWER_CONTROL_SELECT_DDR1_MASK) >> LDO_POWER_CONTROL_SELECT_DDR1_LSB)
#define LDO_POWER_CONTROL_SELECT_DDR1_SET(x)			(((x) << LDO_POWER_CONTROL_SELECT_DDR1_LSB) & LDO_POWER_CONTROL_SELECT_DDR1_MASK)
#define LDO_POWER_CONTROL_SELECT_DDR1_RESET			0x0 // 0
#define LDO_POWER_CONTROL_ADDRESS				0x1805001c

// 0x18050020	SWITCH_CLOCK_SPARE
#define SWITCH_CLOCK_SPARE_SPARE_MSB				31
#define SWITCH_CLOCK_SPARE_SPARE_LSB				16
#define SWITCH_CLOCK_SPARE_SPARE_MASK				0xffff0000
#define SWITCH_CLOCK_SPARE_SPARE_GET(x)				(((x) & SWITCH_CLOCK_SPARE_SPARE_MASK) >> SWITCH_CLOCK_SPARE_SPARE_LSB)
#define SWITCH_CLOCK_SPARE_SPARE_SET(x)				(((x) << SWITCH_CLOCK_SPARE_SPARE_LSB) & SWITCH_CLOCK_SPARE_SPARE_MASK)
#define SWITCH_CLOCK_SPARE_SPARE_RESET				0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MSB			15
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB			15
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK			0x00008000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_GET(x)		(((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_SET(x)		(((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2_RESET		0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MSB			14
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB			14
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK			0x00004000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_GET(x)		(((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_SET(x)		(((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1_RESET		0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MSB			13
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB			13
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK			0x00002000
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_GET(x)		(((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_SET(x)		(((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2_RESET		0x0 // 0
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MSB			12
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB			12
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK			0x00001000
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_GET(x)			(((x) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_SET(x)			(((x) << SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_NANDF_CLK_SEL_RESET			0x0 // 0
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MSB		11
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB		8
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK		0x00000f00
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_GET(x)		(((x) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK) >> SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(x)		(((x) << SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_LSB) & SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)
#define SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_RESET		0x5 // 5
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MSB			7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB			7
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK			0x00000080
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_GET(x)			(((x) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_SET(x)			(((x) << SWITCH_CLOCK_SPARE_UART1_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_UART1_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_UART1_CLK_SEL_RESET			0x0 // 0
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MSB			6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB			6
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK			0x00000040
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_GET(x)		(((x) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK) >> SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_SET(x)		(((x) << SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_LSB) & SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_MASK)
#define SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1_RESET		0x0 // 0
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MSB			5
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB			5
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK			0x00000020
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_GET(x)			(((x) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK) >> SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB)
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_SET(x)			(((x) << SWITCH_CLOCK_SPARE_I2C_CLK_SEL_LSB) & SWITCH_CLOCK_SPARE_I2C_CLK_SEL_MASK)
#define SWITCH_CLOCK_SPARE_I2C_CLK_SEL_RESET			0x0 // 0
#define SWITCH_CLOCK_SPARE_SPARE_0_MSB				4
#define SWITCH_CLOCK_SPARE_SPARE_0_LSB				0
#define SWITCH_CLOCK_SPARE_SPARE_0_MASK				0x0000001f
#define SWITCH_CLOCK_SPARE_SPARE_0_GET(x)			(((x) & SWITCH_CLOCK_SPARE_SPARE_0_MASK) >> SWITCH_CLOCK_SPARE_SPARE_0_LSB)
#define SWITCH_CLOCK_SPARE_SPARE_0_SET(x)			(((x) << SWITCH_CLOCK_SPARE_SPARE_0_LSB) & SWITCH_CLOCK_SPARE_SPARE_0_MASK)
#define SWITCH_CLOCK_SPARE_SPARE_0_RESET			0x0 // 0
#define SWITCH_CLOCK_SPARE_ADDRESS				0x18050020

// 0x18050028	ETH_XMII
#define ETH_XMII_TX_INVERT_MSB					31
#define ETH_XMII_TX_INVERT_LSB					31
#define ETH_XMII_TX_INVERT_MASK					0x80000000
#define ETH_XMII_TX_INVERT_GET(x)				(((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
#define ETH_XMII_TX_INVERT_SET(x)				(((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
#define ETH_XMII_TX_INVERT_RESET				0x0 // 0
#define ETH_XMII_GIGE_QUAD_MSB					30
#define ETH_XMII_GIGE_QUAD_LSB					30
#define ETH_XMII_GIGE_QUAD_MASK					0x40000000
#define ETH_XMII_GIGE_QUAD_GET(x)				(((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
#define ETH_XMII_GIGE_QUAD_SET(x)				(((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
#define ETH_XMII_GIGE_QUAD_RESET				0x0 // 0
#define ETH_XMII_RX_DELAY_MSB					29
#define ETH_XMII_RX_DELAY_LSB					28
#define ETH_XMII_RX_DELAY_MASK					0x30000000
#define ETH_XMII_RX_DELAY_GET(x)				(((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
#define ETH_XMII_RX_DELAY_SET(x)				(((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
#define ETH_XMII_RX_DELAY_RESET					0x0 // 0
#define ETH_XMII_TX_DELAY_MSB					27
#define ETH_XMII_TX_DELAY_LSB					26
#define ETH_XMII_TX_DELAY_MASK					0x0c000000
#define ETH_XMII_TX_DELAY_GET(x)				(((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
#define ETH_XMII_TX_DELAY_SET(x)				(((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
#define ETH_XMII_TX_DELAY_RESET					0x0 // 0
#define ETH_XMII_GIGE_MSB					25
#define ETH_XMII_GIGE_LSB					25
#define ETH_XMII_GIGE_MASK					0x02000000
#define ETH_XMII_GIGE_GET(x)					(((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
#define ETH_XMII_GIGE_SET(x)					(((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
#define ETH_XMII_GIGE_RESET					0x0 // 0
#define ETH_XMII_OFFSET_PHASE_MSB				24
#define ETH_XMII_OFFSET_PHASE_LSB				24
#define ETH_XMII_OFFSET_PHASE_MASK				0x01000000
#define ETH_XMII_OFFSET_PHASE_GET(x)				(((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
#define ETH_XMII_OFFSET_PHASE_SET(x)				(((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
#define ETH_XMII_OFFSET_PHASE_RESET				0x0 // 0
#define ETH_XMII_OFFSET_COUNT_MSB				23
#define ETH_XMII_OFFSET_COUNT_LSB				16
#define ETH_XMII_OFFSET_COUNT_MASK				0x00ff0000
#define ETH_XMII_OFFSET_COUNT_GET(x)				(((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
#define ETH_XMII_OFFSET_COUNT_SET(x)				(((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
#define ETH_XMII_OFFSET_COUNT_RESET				0x0 // 0
#define ETH_XMII_PHASE1_COUNT_MSB				15
#define ETH_XMII_PHASE1_COUNT_LSB				8
#define ETH_XMII_PHASE1_COUNT_MASK				0x0000ff00
#define ETH_XMII_PHASE1_COUNT_GET(x)				(((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
#define ETH_XMII_PHASE1_COUNT_SET(x)				(((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
#define ETH_XMII_PHASE1_COUNT_RESET				0x1 // 1
#define ETH_XMII_PHASE0_COUNT_MSB				7
#define ETH_XMII_PHASE0_COUNT_LSB				0
#define ETH_XMII_PHASE0_COUNT_MASK				0x000000ff
#define ETH_XMII_PHASE0_COUNT_GET(x)				(((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
#define ETH_XMII_PHASE0_COUNT_SET(x)				(((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
#define ETH_XMII_PHASE0_COUNT_RESET				0x1 // 1
#define ETH_XMII_ADDRESS					0x18050028

// 0x18050040	DDR_PLL_DITHER
#define DDR_PLL_DITHER_DITHER_EN_MSB				31
#define DDR_PLL_DITHER_DITHER_EN_LSB				31
#define DDR_PLL_DITHER_DITHER_EN_MASK				0x80000000
#define DDR_PLL_DITHER_DITHER_EN_GET(x)				(((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
#define DDR_PLL_DITHER_DITHER_EN_SET(x)				(((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
#define DDR_PLL_DITHER_DITHER_EN_RESET				0x0 // 0
#define DDR_PLL_DITHER_UPDATE_COUNT_MSB				30
#define DDR_PLL_DITHER_UPDATE_COUNT_LSB				27
#define DDR_PLL_DITHER_UPDATE_COUNT_MASK			0x78000000
#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x)			(((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x)			(((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
#define DDR_PLL_DITHER_UPDATE_COUNT_RESET			0xf // 15
#define DDR_PLL_DITHER_NFRAC_STEP_MSB				26
#define DDR_PLL_DITHER_NFRAC_STEP_LSB				20
#define DDR_PLL_DITHER_NFRAC_STEP_MASK				0x07f00000
#define DDR_PLL_DITHER_NFRAC_STEP_GET(x)			(((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
#define DDR_PLL_DITHER_NFRAC_STEP_SET(x)			(((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
#define DDR_PLL_DITHER_NFRAC_STEP_RESET				0x1 // 1
#define DDR_PLL_DITHER_NFRAC_MIN_MSB				19
#define DDR_PLL_DITHER_NFRAC_MIN_LSB				10
#define DDR_PLL_DITHER_NFRAC_MIN_MASK				0x000ffc00
#define DDR_PLL_DITHER_NFRAC_MIN_GET(x)				(((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
#define DDR_PLL_DITHER_NFRAC_MIN_SET(x)				(((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
#define DDR_PLL_DITHER_NFRAC_MAX_MSB				9
#define DDR_PLL_DITHER_NFRAC_MAX_LSB				0
#define DDR_PLL_DITHER_NFRAC_MAX_MASK				0x000003ff
#define DDR_PLL_DITHER_NFRAC_MAX_GET(x)				(((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
#define DDR_PLL_DITHER_NFRAC_MAX_SET(x)				(((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
#define DDR_PLL_DITHER_ADDRESS					0x18050040

// 0x18050040	DDR_PLL_DITHER
#define DDR_PLL_DITHER_DITHER_EN_MSB				31
#define DDR_PLL_DITHER_DITHER_EN_LSB				31
#define DDR_PLL_DITHER_DITHER_EN_MASK				0x80000000
#define DDR_PLL_DITHER_DITHER_EN_GET(x)				(((x) & DDR_PLL_DITHER_DITHER_EN_MASK) >> DDR_PLL_DITHER_DITHER_EN_LSB)
#define DDR_PLL_DITHER_DITHER_EN_SET(x)				(((x) << DDR_PLL_DITHER_DITHER_EN_LSB) & DDR_PLL_DITHER_DITHER_EN_MASK)
#define DDR_PLL_DITHER_DITHER_EN_RESET				0x0 // 0
#define DDR_PLL_DITHER_UPDATE_COUNT_MSB				30
#define DDR_PLL_DITHER_UPDATE_COUNT_LSB				27
#define DDR_PLL_DITHER_UPDATE_COUNT_MASK			0x78000000
#define DDR_PLL_DITHER_UPDATE_COUNT_GET(x)			(((x) & DDR_PLL_DITHER_UPDATE_COUNT_MASK) >> DDR_PLL_DITHER_UPDATE_COUNT_LSB)
#define DDR_PLL_DITHER_UPDATE_COUNT_SET(x)			(((x) << DDR_PLL_DITHER_UPDATE_COUNT_LSB) & DDR_PLL_DITHER_UPDATE_COUNT_MASK)
#define DDR_PLL_DITHER_UPDATE_COUNT_RESET			0xf // 15
#define DDR_PLL_DITHER_NFRAC_STEP_MSB				26
#define DDR_PLL_DITHER_NFRAC_STEP_LSB				20
#define DDR_PLL_DITHER_NFRAC_STEP_MASK				0x07f00000
#define DDR_PLL_DITHER_NFRAC_STEP_GET(x)			(((x) & DDR_PLL_DITHER_NFRAC_STEP_MASK) >> DDR_PLL_DITHER_NFRAC_STEP_LSB)
#define DDR_PLL_DITHER_NFRAC_STEP_SET(x)			(((x) << DDR_PLL_DITHER_NFRAC_STEP_LSB) & DDR_PLL_DITHER_NFRAC_STEP_MASK)
#define DDR_PLL_DITHER_NFRAC_STEP_RESET				0x1 // 1
#define DDR_PLL_DITHER_NFRAC_MIN_MSB				19
#define DDR_PLL_DITHER_NFRAC_MIN_LSB				10
#define DDR_PLL_DITHER_NFRAC_MIN_MASK				0x000ffc00
#define DDR_PLL_DITHER_NFRAC_MIN_GET(x)				(((x) & DDR_PLL_DITHER_NFRAC_MIN_MASK) >> DDR_PLL_DITHER_NFRAC_MIN_LSB)
#define DDR_PLL_DITHER_NFRAC_MIN_SET(x)				(((x) << DDR_PLL_DITHER_NFRAC_MIN_LSB) & DDR_PLL_DITHER_NFRAC_MIN_MASK)
#define DDR_PLL_DITHER_NFRAC_MAX_MSB				9
#define DDR_PLL_DITHER_NFRAC_MAX_LSB				0
#define DDR_PLL_DITHER_NFRAC_MAX_MASK				0x000003ff
#define DDR_PLL_DITHER_NFRAC_MAX_GET(x)				(((x) & DDR_PLL_DITHER_NFRAC_MAX_MASK) >> DDR_PLL_DITHER_NFRAC_MAX_LSB)
#define DDR_PLL_DITHER_NFRAC_MAX_SET(x)				(((x) << DDR_PLL_DITHER_NFRAC_MAX_LSB) & DDR_PLL_DITHER_NFRAC_MAX_MASK)
#define DDR_PLL_DITHER_ADDRESS					0x18050040

// 0x18050044	CPU_PLL_DITHER
#define CPU_PLL_DITHER_DITHER_EN_MSB				31
#define CPU_PLL_DITHER_DITHER_EN_LSB				31
#define CPU_PLL_DITHER_DITHER_EN_MASK				0x80000000
#define CPU_PLL_DITHER_DITHER_EN_GET(x)				(((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
#define CPU_PLL_DITHER_DITHER_EN_SET(x)				(((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
#define CPU_PLL_DITHER_DITHER_EN_RESET				0x0 // 0
#define CPU_PLL_DITHER_UPDATE_COUNT_MSB				23
#define CPU_PLL_DITHER_UPDATE_COUNT_LSB				18
#define CPU_PLL_DITHER_UPDATE_COUNT_MASK			0x00fc0000
#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x)			(((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x)			(((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
#define CPU_PLL_DITHER_NFRAC_STEP_MSB				17
#define CPU_PLL_DITHER_NFRAC_STEP_LSB				12
#define CPU_PLL_DITHER_NFRAC_STEP_MASK				0x0003f000
#define CPU_PLL_DITHER_NFRAC_STEP_GET(x)			(((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
#define CPU_PLL_DITHER_NFRAC_STEP_SET(x)			(((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
#define CPU_PLL_DITHER_NFRAC_STEP_RESET				0x1 // 1
#define CPU_PLL_DITHER_NFRAC_MIN_MSB				11
#define CPU_PLL_DITHER_NFRAC_MIN_LSB				6
#define CPU_PLL_DITHER_NFRAC_MIN_MASK				0x00000fc0
#define CPU_PLL_DITHER_NFRAC_MIN_GET(x)				(((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
#define CPU_PLL_DITHER_NFRAC_MIN_SET(x)				(((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
#define CPU_PLL_DITHER_NFRAC_MIN_RESET				0x3 // 3
#define CPU_PLL_DITHER_NFRAC_MAX_MSB				5
#define CPU_PLL_DITHER_NFRAC_MAX_LSB				0
#define CPU_PLL_DITHER_NFRAC_MAX_MASK				0x0000003f
#define CPU_PLL_DITHER_NFRAC_MAX_GET(x)				(((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
#define CPU_PLL_DITHER_NFRAC_MAX_SET(x)				(((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
#define CPU_PLL_DITHER_ADDRESS					0x18050044

// 0x18050044	CPU_PLL_DITHER
#define CPU_PLL_DITHER_DITHER_EN_MSB				31
#define CPU_PLL_DITHER_DITHER_EN_LSB				31
#define CPU_PLL_DITHER_DITHER_EN_MASK				0x80000000
#define CPU_PLL_DITHER_DITHER_EN_GET(x)				(((x) & CPU_PLL_DITHER_DITHER_EN_MASK) >> CPU_PLL_DITHER_DITHER_EN_LSB)
#define CPU_PLL_DITHER_DITHER_EN_SET(x)				(((x) << CPU_PLL_DITHER_DITHER_EN_LSB) & CPU_PLL_DITHER_DITHER_EN_MASK)
#define CPU_PLL_DITHER_DITHER_EN_RESET				0x0 // 0
#define CPU_PLL_DITHER_UPDATE_COUNT_MSB				23
#define CPU_PLL_DITHER_UPDATE_COUNT_LSB				18
#define CPU_PLL_DITHER_UPDATE_COUNT_MASK			0x00fc0000
#define CPU_PLL_DITHER_UPDATE_COUNT_GET(x)			(((x) & CPU_PLL_DITHER_UPDATE_COUNT_MASK) >> CPU_PLL_DITHER_UPDATE_COUNT_LSB)
#define CPU_PLL_DITHER_UPDATE_COUNT_SET(x)			(((x) << CPU_PLL_DITHER_UPDATE_COUNT_LSB) & CPU_PLL_DITHER_UPDATE_COUNT_MASK)
#define CPU_PLL_DITHER_NFRAC_STEP_MSB				17
#define CPU_PLL_DITHER_NFRAC_STEP_LSB				12
#define CPU_PLL_DITHER_NFRAC_STEP_MASK				0x0003f000
#define CPU_PLL_DITHER_NFRAC_STEP_GET(x)			(((x) & CPU_PLL_DITHER_NFRAC_STEP_MASK) >> CPU_PLL_DITHER_NFRAC_STEP_LSB)
#define CPU_PLL_DITHER_NFRAC_STEP_SET(x)			(((x) << CPU_PLL_DITHER_NFRAC_STEP_LSB) & CPU_PLL_DITHER_NFRAC_STEP_MASK)
#define CPU_PLL_DITHER_NFRAC_STEP_RESET				0x1 // 1
#define CPU_PLL_DITHER_NFRAC_MIN_MSB				11
#define CPU_PLL_DITHER_NFRAC_MIN_LSB				6
#define CPU_PLL_DITHER_NFRAC_MIN_MASK				0x00000fc0
#define CPU_PLL_DITHER_NFRAC_MIN_GET(x)				(((x) & CPU_PLL_DITHER_NFRAC_MIN_MASK) >> CPU_PLL_DITHER_NFRAC_MIN_LSB)
#define CPU_PLL_DITHER_NFRAC_MIN_SET(x)				(((x) << CPU_PLL_DITHER_NFRAC_MIN_LSB) & CPU_PLL_DITHER_NFRAC_MIN_MASK)
#define CPU_PLL_DITHER_NFRAC_MIN_RESET				0x3 // 3
#define CPU_PLL_DITHER_NFRAC_MAX_MSB				5
#define CPU_PLL_DITHER_NFRAC_MAX_LSB				0
#define CPU_PLL_DITHER_NFRAC_MAX_MASK				0x0000003f
#define CPU_PLL_DITHER_NFRAC_MAX_GET(x)				(((x) & CPU_PLL_DITHER_NFRAC_MAX_MASK) >> CPU_PLL_DITHER_NFRAC_MAX_LSB)
#define CPU_PLL_DITHER_NFRAC_MAX_SET(x)				(((x) << CPU_PLL_DITHER_NFRAC_MAX_LSB) & CPU_PLL_DITHER_NFRAC_MAX_MASK)
#define CPU_PLL_DITHER_ADDRESS					0x18050044

// 0x18050048	ETH_SGMII
#define ETH_SGMII_TX_INVERT_MSB					31
#define ETH_SGMII_TX_INVERT_LSB					31
#define ETH_SGMII_TX_INVERT_MASK				0x80000000
#define ETH_SGMII_TX_INVERT_GET(x)				(((x) & ETH_SGMII_TX_INVERT_MASK) >> ETH_SGMII_TX_INVERT_LSB)
#define ETH_SGMII_TX_INVERT_SET(x)				(((x) << ETH_SGMII_TX_INVERT_LSB) & ETH_SGMII_TX_INVERT_MASK)
#define ETH_SGMII_TX_INVERT_RESET				0x0 // 0
#define ETH_SGMII_GIGE_QUAD_MSB					30
#define ETH_SGMII_GIGE_QUAD_LSB					30
#define ETH_SGMII_GIGE_QUAD_MASK				0x40000000
#define ETH_SGMII_GIGE_QUAD_GET(x)				(((x) & ETH_SGMII_GIGE_QUAD_MASK) >> ETH_SGMII_GIGE_QUAD_LSB)
#define ETH_SGMII_GIGE_QUAD_SET(x)				(((x) << ETH_SGMII_GIGE_QUAD_LSB) & ETH_SGMII_GIGE_QUAD_MASK)
#define ETH_SGMII_GIGE_QUAD_RESET				0x0 // 0
#define ETH_SGMII_RX_DELAY_MSB					29
#define ETH_SGMII_RX_DELAY_LSB					28
#define ETH_SGMII_RX_DELAY_MASK					0x30000000
#define ETH_SGMII_RX_DELAY_GET(x)				(((x) & ETH_SGMII_RX_DELAY_MASK) >> ETH_SGMII_RX_DELAY_LSB)
#define ETH_SGMII_RX_DELAY_SET(x)				(((x) << ETH_SGMII_RX_DELAY_LSB) & ETH_SGMII_RX_DELAY_MASK)
#define ETH_SGMII_RX_DELAY_RESET				0x0 // 0
#define ETH_SGMII_TX_DELAY_MSB					27
#define ETH_SGMII_TX_DELAY_LSB					26
#define ETH_SGMII_TX_DELAY_MASK					0x0c000000
#define ETH_SGMII_TX_DELAY_GET(x)				(((x) & ETH_SGMII_TX_DELAY_MASK) >> ETH_SGMII_TX_DELAY_LSB)
#define ETH_SGMII_TX_DELAY_SET(x)				(((x) << ETH_SGMII_TX_DELAY_LSB) & ETH_SGMII_TX_DELAY_MASK)
#define ETH_SGMII_TX_DELAY_RESET				0x0 // 0
#define ETH_SGMII_CLK_SEL_MSB					25
#define ETH_SGMII_CLK_SEL_LSB					25
#define ETH_SGMII_CLK_SEL_MASK					0x02000000
#define ETH_SGMII_CLK_SEL_GET(x)				(((x) & ETH_SGMII_CLK_SEL_MASK) >> ETH_SGMII_CLK_SEL_LSB)
#define ETH_SGMII_CLK_SEL_SET(x)				(((x) << ETH_SGMII_CLK_SEL_LSB) & ETH_SGMII_CLK_SEL_MASK)
#define ETH_SGMII_CLK_SEL_RESET					0x1 // 1
#define ETH_SGMII_GIGE_MSB					24
#define ETH_SGMII_GIGE_LSB					24
#define ETH_SGMII_GIGE_MASK					0x01000000
#define ETH_SGMII_GIGE_GET(x)					(((x) & ETH_SGMII_GIGE_MASK) >> ETH_SGMII_GIGE_LSB)
#define ETH_SGMII_GIGE_SET(x)					(((x) << ETH_SGMII_GIGE_LSB) & ETH_SGMII_GIGE_MASK)
#define ETH_SGMII_GIGE_RESET					0x1 // 1
#define ETH_SGMII_PHASE1_COUNT_MSB				15
#define ETH_SGMII_PHASE1_COUNT_LSB				8
#define ETH_SGMII_PHASE1_COUNT_MASK				0x0000ff00
#define ETH_SGMII_PHASE1_COUNT_GET(x)				(((x) & ETH_SGMII_PHASE1_COUNT_MASK) >> ETH_SGMII_PHASE1_COUNT_LSB)
#define ETH_SGMII_PHASE1_COUNT_SET(x)				(((x) << ETH_SGMII_PHASE1_COUNT_LSB) & ETH_SGMII_PHASE1_COUNT_MASK)
#define ETH_SGMII_PHASE1_COUNT_RESET				0x1 // 1
#define ETH_SGMII_PHASE0_COUNT_MSB				7
#define ETH_SGMII_PHASE0_COUNT_LSB				0
#define ETH_SGMII_PHASE0_COUNT_MASK				0x000000ff
#define ETH_SGMII_PHASE0_COUNT_GET(x)				(((x) & ETH_SGMII_PHASE0_COUNT_MASK) >> ETH_SGMII_PHASE0_COUNT_LSB)
#define ETH_SGMII_PHASE0_COUNT_SET(x)				(((x) << ETH_SGMII_PHASE0_COUNT_LSB) & ETH_SGMII_PHASE0_COUNT_MASK)
#define ETH_SGMII_PHASE0_COUNT_RESET				0x1 // 1
#define ETH_SGMII_ADDRESS					0x18050048

// 0x1805004c	ETH_SGMII_SERDES
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MSB			2
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB			2
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK			0x00000004
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_GET(x)			(((x) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK) >> ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB)
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_SET(x)			(((x) << ETH_SGMII_SERDES_EN_LOCK_DETECT_LSB) & ETH_SGMII_SERDES_EN_LOCK_DETECT_MASK)
#define ETH_SGMII_SERDES_EN_LOCK_DETECT_RESET			0x0 // 0
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MSB			1
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB			1
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK			0x00000002
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_GET(x)			(((x) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK) >> ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB)
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_SET(x)			(((x) << ETH_SGMII_SERDES_PLL_REFCLK_SEL_LSB) & ETH_SGMII_SERDES_PLL_REFCLK_SEL_MASK)
#define ETH_SGMII_SERDES_PLL_REFCLK_SEL_RESET			0x0 // 0
#define ETH_SGMII_SERDES_EN_PLL_MSB				0
#define ETH_SGMII_SERDES_EN_PLL_LSB				0
#define ETH_SGMII_SERDES_EN_PLL_MASK				0x00000001
#define ETH_SGMII_SERDES_EN_PLL_GET(x)				(((x) & ETH_SGMII_SERDES_EN_PLL_MASK) >> ETH_SGMII_SERDES_EN_PLL_LSB)
#define ETH_SGMII_SERDES_EN_PLL_SET(x)				(((x) << ETH_SGMII_SERDES_EN_PLL_LSB) & ETH_SGMII_SERDES_EN_PLL_MASK)
#define ETH_SGMII_SERDES_EN_PLL_RESET				0x1 // 1
#define ETH_SGMII_SERDES_ADDRESS				0x1805004c

// 0x18050050	SLIC_PWM_DIV
#define SLIC_PWM_DIV_ENABLE_MSB					31
#define SLIC_PWM_DIV_ENABLE_LSB					31
#define SLIC_PWM_DIV_ENABLE_MASK				0x80000000
#define SLIC_PWM_DIV_ENABLE_GET(x)				(((x) & SLIC_PWM_DIV_ENABLE_MASK) >> SLIC_PWM_DIV_ENABLE_LSB)
#define SLIC_PWM_DIV_ENABLE_SET(x)				(((x) << SLIC_PWM_DIV_ENABLE_LSB) & SLIC_PWM_DIV_ENABLE_MASK)
#define SLIC_PWM_DIV_ENABLE_RESET				0x0 // 0
#define SLIC_PWM_DIV_REFCLK_MSB					30
#define SLIC_PWM_DIV_REFCLK_LSB					30
#define SLIC_PWM_DIV_REFCLK_MASK				0x40000000
#define SLIC_PWM_DIV_REFCLK_GET(x)				(((x) & SLIC_PWM_DIV_REFCLK_MASK) >> SLIC_PWM_DIV_REFCLK_LSB)
#define SLIC_PWM_DIV_REFCLK_SET(x)				(((x) << SLIC_PWM_DIV_REFCLK_LSB) & SLIC_PWM_DIV_REFCLK_MASK)
#define SLIC_PWM_DIV_REFCLK_RESET				0x0 // 0
#define SLIC_PWM_DIV_SPARE_MSB					29
#define SLIC_PWM_DIV_SPARE_LSB					16
#define SLIC_PWM_DIV_SPARE_MASK					0x3fff0000
#define SLIC_PWM_DIV_SPARE_GET(x)				(((x) & SLIC_PWM_DIV_SPARE_MASK) >> SLIC_PWM_DIV_SPARE_LSB)
#define SLIC_PWM_DIV_SPARE_SET(x)				(((x) << SLIC_PWM_DIV_SPARE_LSB) & SLIC_PWM_DIV_SPARE_MASK)
#define SLIC_PWM_DIV_SPARE_RESET				0x0 // 0
#define SLIC_PWM_DIV_PHASE1_COUNT_MSB				15
#define SLIC_PWM_DIV_PHASE1_COUNT_LSB				8
#define SLIC_PWM_DIV_PHASE1_COUNT_MASK				0x0000ff00
#define SLIC_PWM_DIV_PHASE1_COUNT_GET(x)			(((x) & SLIC_PWM_DIV_PHASE1_COUNT_MASK) >> SLIC_PWM_DIV_PHASE1_COUNT_LSB)
#define SLIC_PWM_DIV_PHASE1_COUNT_SET(x)			(((x) << SLIC_PWM_DIV_PHASE1_COUNT_LSB) & SLIC_PWM_DIV_PHASE1_COUNT_MASK)
#define SLIC_PWM_DIV_PHASE1_COUNT_RESET				0x1 // 1
#define SLIC_PWM_DIV_PHASE0_COUNT_MSB				7
#define SLIC_PWM_DIV_PHASE0_COUNT_LSB				0
#define SLIC_PWM_DIV_PHASE0_COUNT_MASK				0x000000ff
#define SLIC_PWM_DIV_PHASE0_COUNT_GET(x)			(((x) & SLIC_PWM_DIV_PHASE0_COUNT_MASK) >> SLIC_PWM_DIV_PHASE0_COUNT_LSB)
#define SLIC_PWM_DIV_PHASE0_COUNT_SET(x)			(((x) << SLIC_PWM_DIV_PHASE0_COUNT_LSB) & SLIC_PWM_DIV_PHASE0_COUNT_MASK)
#define SLIC_PWM_DIV_PHASE0_COUNT_RESET				0x1 // 1
#define SLIC_PWM_DIV_ADDRESS					0x18050050

// 0x18060000	RST_GENERAL_TIMER1
#define RST_GENERAL_TIMER1_TIMER_MSB				31
#define RST_GENERAL_TIMER1_TIMER_LSB				0
#define RST_GENERAL_TIMER1_TIMER_MASK				0xffffffff
#define RST_GENERAL_TIMER1_TIMER_GET(x)				(((x) & RST_GENERAL_TIMER1_TIMER_MASK) >> RST_GENERAL_TIMER1_TIMER_LSB)
#define RST_GENERAL_TIMER1_TIMER_SET(x)				(((x) << RST_GENERAL_TIMER1_TIMER_LSB) & RST_GENERAL_TIMER1_TIMER_MASK)
#define RST_GENERAL_TIMER1_TIMER_RESET				0x0 // 0
#define RST_GENERAL_TIMER1_ADDRESS				0x18060000

// 0x18060004	RST_GENERAL_TIMER1_RELOAD
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_MSB		31
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_LSB		0
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_MASK		0xffffffff
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_GET(x)		(((x) & RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_MASK) >> RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_LSB)
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_SET(x)		(((x) << RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_LSB) & RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_MASK)
#define RST_GENERAL_TIMER1_RELOAD_RELOAD_VALUE1_RESET		0x0 // 0
#define RST_GENERAL_TIMER1_RELOAD_ADDRESS			0x18060004

// 0x18060008	RST_WATCHDOG_TIMER_CONTROL
#define RST_WATCHDOG_TIMER_CONTROL_LAST_MSB			31
#define RST_WATCHDOG_TIMER_CONTROL_LAST_LSB			31
#define RST_WATCHDOG_TIMER_CONTROL_LAST_MASK			0x80000000
#define RST_WATCHDOG_TIMER_CONTROL_LAST_GET(x)			(((x) & RST_WATCHDOG_TIMER_CONTROL_LAST_MASK) >> RST_WATCHDOG_TIMER_CONTROL_LAST_LSB)
#define RST_WATCHDOG_TIMER_CONTROL_LAST_SET(x)			(((x) << RST_WATCHDOG_TIMER_CONTROL_LAST_LSB) & RST_WATCHDOG_TIMER_CONTROL_LAST_MASK)
#define RST_WATCHDOG_TIMER_CONTROL_LAST_RESET			0x0 // 0
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_MSB			1
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_LSB			0
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_MASK			0x00000003
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_GET(x)		(((x) & RST_WATCHDOG_TIMER_CONTROL_ACTION_MASK) >> RST_WATCHDOG_TIMER_CONTROL_ACTION_LSB)
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_SET(x)		(((x) << RST_WATCHDOG_TIMER_CONTROL_ACTION_LSB) & RST_WATCHDOG_TIMER_CONTROL_ACTION_MASK)
#define RST_WATCHDOG_TIMER_CONTROL_ACTION_RESET			0x0 // 0
#define RST_WATCHDOG_TIMER_CONTROL_ADDRESS			0x18060008

// 0x1806000c	RST_WATCHDOG_TIMER
#define RST_WATCHDOG_TIMER_TIMER_MSB				31
#define RST_WATCHDOG_TIMER_TIMER_LSB				0
#define RST_WATCHDOG_TIMER_TIMER_MASK				0xffffffff
#define RST_WATCHDOG_TIMER_TIMER_GET(x)				(((x) & RST_WATCHDOG_TIMER_TIMER_MASK) >> RST_WATCHDOG_TIMER_TIMER_LSB)
#define RST_WATCHDOG_TIMER_TIMER_SET(x)				(((x) << RST_WATCHDOG_TIMER_TIMER_LSB) & RST_WATCHDOG_TIMER_TIMER_MASK)
#define RST_WATCHDOG_TIMER_TIMER_RESET				0x0 // 0
#define RST_WATCHDOG_TIMER_ADDRESS				0x1806000c

// 0x18060010	RST_MISC_INTERRUPT_STATUS
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_MSB		26
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_LSB		26
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_MASK		0x04000000
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_MASK) >> RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_LSB)
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_LSB) & RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_MASK)
#define RST_MISC_INTERRUPT_STATUS_USB2_PLL_LOCK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_MSB		25
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_LSB		25
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_MASK		0x02000000
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_MASK) >> RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_LSB)
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_LSB) & RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_MASK)
#define RST_MISC_INTERRUPT_STATUS_USB1_PLL_LOCK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_MSB			24
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_LSB			24
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_MASK			0x01000000
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_I2C_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_I2C_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_I2C_INT_LSB) & RST_MISC_INTERRUPT_STATUS_I2C_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_I2C_INT_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_MSB			23
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_LSB			23
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_MASK			0x00800000
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_FDC_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_FDC_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_FDC_INT_LSB) & RST_MISC_INTERRUPT_STATUS_FDC_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_FDC_INT_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_MSB			22
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_LSB			22
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_MASK		0x00400000
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_PGPIO_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_PGPIO_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_PGPIO_INT_LSB) & RST_MISC_INTERRUPT_STATUS_PGPIO_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_PGPIO_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_MSB		21
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_LSB		21
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_MASK		0x00200000
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_NANDF_INTR_MASK) >> RST_MISC_INTERRUPT_STATUS_NANDF_INTR_LSB)
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_NANDF_INTR_LSB) & RST_MISC_INTERRUPT_STATUS_NANDF_INTR_MASK)
#define RST_MISC_INTERRUPT_STATUS_NANDF_INTR_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_MSB			20
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_LSB			20
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_MASK			0x00100000
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_WOW_INTR_MASK) >> RST_MISC_INTERRUPT_STATUS_WOW_INTR_LSB)
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_WOW_INTR_LSB) & RST_MISC_INTERRUPT_STATUS_WOW_INTR_MASK)
#define RST_MISC_INTERRUPT_STATUS_WOW_INTR_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_MSB			19
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_LSB			19
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_MASK		0x00080000
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_SLIC_INTR_MASK) >> RST_MISC_INTERRUPT_STATUS_SLIC_INTR_LSB)
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_SLIC_INTR_LSB) & RST_MISC_INTERRUPT_STATUS_SLIC_INTR_MASK)
#define RST_MISC_INTERRUPT_STATUS_SLIC_INTR_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_MSB	18
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_LSB	18
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_MASK	0x00040000
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_GET(x)	(((x) & RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_MASK) >> RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_LSB)
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_SET(x)	(((x) << RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_LSB) & RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_MASK)
#define RST_MISC_INTERRUPT_STATUS_DDR_ACTIVITY_IN_SF_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_MSB		17
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_LSB		17
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_MASK		0x00020000
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_MASK) >> RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_LSB)
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_LSB) & RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_MASK)
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_EXIT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_MSB		16
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_LSB		16
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_MASK		0x00010000
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_MASK) >> RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_LSB)
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_LSB) & RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_MASK)
#define RST_MISC_INTERRUPT_STATUS_DDR_SF_ENTRY_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_MSB		15
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_LSB		15
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_MASK		0x00008000
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_LSB) & RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_CHKSUM_ACC_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_MSB			14
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_LSB			14
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_MASK			0x00004000
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_OTP_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_OTP_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_OTP_INT_LSB) & RST_MISC_INTERRUPT_STATUS_OTP_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_OTP_INT_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_MSB		13
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_LSB		13
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_MASK		0x00002000
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_LSB) & RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_LUTS_AGER_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_MSB		12
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_LSB		12
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_MASK		0x00001000
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_LSB) & RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_SGMII_MAC_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_MSB		11
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_LSB		11
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_MASK		0x00000800
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_LSB) & RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_DDR_PERF_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_MSB		10
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_LSB		10
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_MASK		0x00000400
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_TIMER4_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_TIMER4_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_TIMER4_INT_LSB) & RST_MISC_INTERRUPT_STATUS_TIMER4_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_TIMER4_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_MSB		9
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_LSB		9
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_MASK		0x00000200
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_TIMER3_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_TIMER3_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_TIMER3_INT_LSB) & RST_MISC_INTERRUPT_STATUS_TIMER3_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_TIMER3_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_MSB		8
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_LSB		8
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_MASK		0x00000100
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_TIMER2_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_TIMER2_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_TIMER2_INT_LSB) & RST_MISC_INTERRUPT_STATUS_TIMER2_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_TIMER2_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_MSB			7
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_LSB			7
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_MASK			0x00000080
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_MBOX_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_MBOX_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_MBOX_INT_LSB) & RST_MISC_INTERRUPT_STATUS_MBOX_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_MBOX_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_MSB			6
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_LSB			6
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_MASK		0x00000040
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_UART1_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_UART1_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_UART1_INT_LSB) & RST_MISC_INTERRUPT_STATUS_UART1_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_UART1_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_PC_INT_MSB			5
#define RST_MISC_INTERRUPT_STATUS_PC_INT_LSB			5
#define RST_MISC_INTERRUPT_STATUS_PC_INT_MASK			0x00000020
#define RST_MISC_INTERRUPT_STATUS_PC_INT_GET(x)			(((x) & RST_MISC_INTERRUPT_STATUS_PC_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_PC_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_PC_INT_SET(x)			(((x) << RST_MISC_INTERRUPT_STATUS_PC_INT_LSB) & RST_MISC_INTERRUPT_STATUS_PC_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_PC_INT_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_MSB		4
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_LSB		4
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_MASK		0x00000010
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_LSB) & RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_WATCHDOG_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_UART_INT_MSB			3
#define RST_MISC_INTERRUPT_STATUS_UART_INT_LSB			3
#define RST_MISC_INTERRUPT_STATUS_UART_INT_MASK			0x00000008
#define RST_MISC_INTERRUPT_STATUS_UART_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_UART_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_UART_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_UART_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_UART_INT_LSB) & RST_MISC_INTERRUPT_STATUS_UART_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_UART_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_MSB			2
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_LSB			2
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_MASK			0x00000004
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_GPIO_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_GPIO_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_GPIO_INT_LSB) & RST_MISC_INTERRUPT_STATUS_GPIO_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_GPIO_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_MSB			1
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_LSB			1
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_MASK		0x00000002
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_ERROR_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_ERROR_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_ERROR_INT_LSB) & RST_MISC_INTERRUPT_STATUS_ERROR_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_ERROR_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_MSB			0
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_LSB			0
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_MASK		0x00000001
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_GET(x)		(((x) & RST_MISC_INTERRUPT_STATUS_TIMER_INT_MASK) >> RST_MISC_INTERRUPT_STATUS_TIMER_INT_LSB)
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_SET(x)		(((x) << RST_MISC_INTERRUPT_STATUS_TIMER_INT_LSB) & RST_MISC_INTERRUPT_STATUS_TIMER_INT_MASK)
#define RST_MISC_INTERRUPT_STATUS_TIMER_INT_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_STATUS_ADDRESS			0x18060010

// 0x18060014	RST_MISC_INTERRUPT_MASK
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_MSB		26
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_LSB		26
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_MASK		0x04000000
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_LSB) & RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_USB2_PLL_LOCK_MASK_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_MSB		25
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_LSB		25
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_MASK		0x02000000
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_LSB) & RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_USB1_PLL_LOCK_MASK_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_MSB			24
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_LSB			24
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_MASK			0x01000000
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_GET(x)			(((x) & RST_MISC_INTERRUPT_MASK_I2C_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_I2C_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_SET(x)			(((x) << RST_MISC_INTERRUPT_MASK_I2C_MASK_LSB) & RST_MISC_INTERRUPT_MASK_I2C_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_I2C_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_MSB			23
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_LSB			23
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_MASK			0x00800000
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_GET(x)			(((x) & RST_MISC_INTERRUPT_MASK_FDC_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_FDC_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_SET(x)			(((x) << RST_MISC_INTERRUPT_MASK_FDC_MASK_LSB) & RST_MISC_INTERRUPT_MASK_FDC_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_FDC_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_MSB		22
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_LSB		22
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_MASK		0x00400000
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_LSB) & RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_PGPIO_INT_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_MSB		21
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_LSB		21
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_MASK		0x00200000
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_LSB) & RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_NANDF_INTR_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_MSB		20
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_LSB		20
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_MASK		0x00100000
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_LSB) & RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_WOW_INTR_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_MSB		19
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_LSB		19
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_MASK		0x00080000
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_LSB) & RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_SLIC_INTR_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_MSB	18
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_LSB	18
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_MASK	0x00040000
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_LSB) & RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_DDR_ACTIVITY_IN_SF_MASK_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_MSB		17
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_LSB		17
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_MASK		0x00020000
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_LSB) & RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_DDR_SF_EXIT_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_MSB		16
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_LSB		16
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_MASK		0x00010000
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_LSB) & RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_DDR_SF_ENTRY_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_MSB		15
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_LSB		15
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_MASK		0x00008000
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_LSB) & RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_CHKSUM_ACC_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_MSB		14
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_LSB		14
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_MASK		0x00004000
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_LSB) & RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_OTP_INT_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_MSB		13
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_LSB		13
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_MASK		0x00002000
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_LSB) & RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_LUTS_AGER_INT_MASK_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_MSB		12
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_LSB		12
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_MASK		0x00001000
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_GET(x)	(((x) & RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_SET(x)	(((x) << RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_LSB) & RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_SGMII_MAC_INT_MASK_RESET	0x0 // 0
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_MSB		11
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_LSB		11
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_MASK		0x00000800
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_LSB) & RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_DDR_PERF_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_MSB			10
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_LSB			10
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_MASK		0x00000400
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_TIMER4_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_TIMER4_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_TIMER4_MASK_LSB) & RST_MISC_INTERRUPT_MASK_TIMER4_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_TIMER4_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_MSB			9
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_LSB			9
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_MASK		0x00000200
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_TIMER3_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_TIMER3_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_TIMER3_MASK_LSB) & RST_MISC_INTERRUPT_MASK_TIMER3_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_TIMER3_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_MSB			8
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_LSB			8
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_MASK		0x00000100
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_TIMER2_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_TIMER2_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_TIMER2_MASK_LSB) & RST_MISC_INTERRUPT_MASK_TIMER2_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_TIMER2_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_MSB			7
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_LSB			7
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_MASK			0x00000080
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_MBOX_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_MBOX_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_MBOX_MASK_LSB) & RST_MISC_INTERRUPT_MASK_MBOX_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_MBOX_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_MSB			6
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_LSB			6
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_MASK			0x00000040
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_UART1_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_UART1_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_UART1_MASK_LSB) & RST_MISC_INTERRUPT_MASK_UART1_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_UART1_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_PC_MASK_MSB			5
#define RST_MISC_INTERRUPT_MASK_PC_MASK_LSB			5
#define RST_MISC_INTERRUPT_MASK_PC_MASK_MASK			0x00000020
#define RST_MISC_INTERRUPT_MASK_PC_MASK_GET(x)			(((x) & RST_MISC_INTERRUPT_MASK_PC_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_PC_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_PC_MASK_SET(x)			(((x) << RST_MISC_INTERRUPT_MASK_PC_MASK_LSB) & RST_MISC_INTERRUPT_MASK_PC_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_PC_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_MSB		4
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_LSB		4
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_MASK		0x00000010
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_LSB) & RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_WATCHDOG_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_UART_MASK_MSB			3
#define RST_MISC_INTERRUPT_MASK_UART_MASK_LSB			3
#define RST_MISC_INTERRUPT_MASK_UART_MASK_MASK			0x00000008
#define RST_MISC_INTERRUPT_MASK_UART_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_UART_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_UART_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_UART_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_UART_MASK_LSB) & RST_MISC_INTERRUPT_MASK_UART_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_UART_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_MSB			2
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_LSB			2
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_MASK			0x00000004
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_GPIO_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_GPIO_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_GPIO_MASK_LSB) & RST_MISC_INTERRUPT_MASK_GPIO_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_GPIO_MASK_RESET			0x0 // 0
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_MSB			1
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_LSB			1
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_MASK			0x00000002
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_ERROR_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_ERROR_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_ERROR_MASK_LSB) & RST_MISC_INTERRUPT_MASK_ERROR_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_ERROR_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_MSB			0
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_LSB			0
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_MASK			0x00000001
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_GET(x)		(((x) & RST_MISC_INTERRUPT_MASK_TIMER_MASK_MASK) >> RST_MISC_INTERRUPT_MASK_TIMER_MASK_LSB)
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_SET(x)		(((x) << RST_MISC_INTERRUPT_MASK_TIMER_MASK_LSB) & RST_MISC_INTERRUPT_MASK_TIMER_MASK_MASK)
#define RST_MISC_INTERRUPT_MASK_TIMER_MASK_RESET		0x0 // 0
#define RST_MISC_INTERRUPT_MASK_ADDRESS				0x18060014

// 0x18060018	RST_GLOBAL_INTERRUPT_STATUS
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_MSB		9
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_LSB		9
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_MASK		0x00000200
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_WMAC_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_MSB		8
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_LSB		8
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_MASK		0x00000100
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_RC2_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_MSB		7
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_LSB		7
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_MASK		0x00000080
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_USB2_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_MSB		6
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_LSB		6
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_MASK		0x00000040
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_EP_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_MSB		5
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_LSB		5
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_MASK		0x00000020
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_TIMER_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_MSB		4
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_LSB		4
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_MASK		0x00000010
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_MISC_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_MSB			3
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_LSB			3
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_MASK		0x00000008
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_GE1_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_MSB			2
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_LSB			2
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_MASK		0x00000004
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_GE0_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_MSB		1
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_LSB		1
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_MASK		0x00000002
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_USB1_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_MSB		0
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_LSB		0
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_MASK		0x00000001
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_GET(x)		(((x) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_MASK) >> RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_LSB)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_SET(x)		(((x) << RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_LSB) & RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_MASK)
#define RST_GLOBAL_INTERRUPT_STATUS_PCIE_INT_RESET		0x0 // 0
#define RST_GLOBAL_INTERRUPT_STATUS_ADDRESS			0x18060018

// 0x1806001c	RST_RESET
#define RST_RESET_HOST_RESET_MSB				31
#define RST_RESET_HOST_RESET_LSB				31
#define RST_RESET_HOST_RESET_MASK				0x80000000
#define RST_RESET_HOST_RESET_GET(x)				(((x) & RST_RESET_HOST_RESET_MASK) >> RST_RESET_HOST_RESET_LSB)
#define RST_RESET_HOST_RESET_SET(x)				(((x) << RST_RESET_HOST_RESET_LSB) & RST_RESET_HOST_RESET_MASK)
#define RST_RESET_HOST_RESET_RESET				0x0 // 0
#define RST_RESET_SLIC_RESET_MSB				30
#define RST_RESET_SLIC_RESET_LSB				30
#define RST_RESET_SLIC_RESET_MASK				0x40000000
#define RST_RESET_SLIC_RESET_GET(x)				(((x) & RST_RESET_SLIC_RESET_MASK) >> RST_RESET_SLIC_RESET_LSB)
#define RST_RESET_SLIC_RESET_SET(x)				(((x) << RST_RESET_SLIC_RESET_LSB) & RST_RESET_SLIC_RESET_MASK)
#define RST_RESET_SLIC_RESET_RESET				0x0 // 0
#define RST_RESET_HDMA_RESET_MSB				29
#define RST_RESET_HDMA_RESET_LSB				29
#define RST_RESET_HDMA_RESET_MASK				0x20000000
#define RST_RESET_HDMA_RESET_GET(x)				(((x) & RST_RESET_HDMA_RESET_MASK) >> RST_RESET_HDMA_RESET_LSB)
#define RST_RESET_HDMA_RESET_SET(x)				(((x) << RST_RESET_HDMA_RESET_LSB) & RST_RESET_HDMA_RESET_MASK)
#define RST_RESET_HDMA_RESET_RESET				0x1 // 1
#define RST_RESET_EXTERNAL_RESET_MSB				28
#define RST_RESET_EXTERNAL_RESET_LSB				28
#define RST_RESET_EXTERNAL_RESET_MASK				0x10000000
#define RST_RESET_EXTERNAL_RESET_GET(x)				(((x) & RST_RESET_EXTERNAL_RESET_MASK) >> RST_RESET_EXTERNAL_RESET_LSB)
#define RST_RESET_EXTERNAL_RESET_SET(x)				(((x) << RST_RESET_EXTERNAL_RESET_LSB) & RST_RESET_EXTERNAL_RESET_MASK)
#define RST_RESET_EXTERNAL_RESET_RESET				0x0 // 0
#define RST_RESET_RTC_RESET_MSB					27
#define RST_RESET_RTC_RESET_LSB					27
#define RST_RESET_RTC_RESET_MASK				0x08000000
#define RST_RESET_RTC_RESET_GET(x)				(((x) & RST_RESET_RTC_RESET_MASK) >> RST_RESET_RTC_RESET_LSB)
#define RST_RESET_RTC_RESET_SET(x)				(((x) << RST_RESET_RTC_RESET_LSB) & RST_RESET_RTC_RESET_MASK)
#define RST_RESET_RTC_RESET_RESET				0x1 // 1
#define RST_RESET_PCIEEP_RST_INT_MSB				26
#define RST_RESET_PCIEEP_RST_INT_LSB				26
#define RST_RESET_PCIEEP_RST_INT_MASK				0x04000000
#define RST_RESET_PCIEEP_RST_INT_GET(x)				(((x) & RST_RESET_PCIEEP_RST_INT_MASK) >> RST_RESET_PCIEEP_RST_INT_LSB)
#define RST_RESET_PCIEEP_RST_INT_SET(x)				(((x) << RST_RESET_PCIEEP_RST_INT_LSB) & RST_RESET_PCIEEP_RST_INT_MASK)
#define RST_RESET_PCIEEP_RST_INT_RESET				0x0 // 0
#define RST_RESET_CHKSUM_ACC_RESET_MSB				25
#define RST_RESET_CHKSUM_ACC_RESET_LSB				25
#define RST_RESET_CHKSUM_ACC_RESET_MASK				0x02000000
#define RST_RESET_CHKSUM_ACC_RESET_GET(x)			(((x) & RST_RESET_CHKSUM_ACC_RESET_MASK) >> RST_RESET_CHKSUM_ACC_RESET_LSB)
#define RST_RESET_CHKSUM_ACC_RESET_SET(x)			(((x) << RST_RESET_CHKSUM_ACC_RESET_LSB) & RST_RESET_CHKSUM_ACC_RESET_MASK)
#define RST_RESET_CHKSUM_ACC_RESET_RESET			0x0 // 0
#define RST_RESET_FULL_CHIP_RESET_MSB				24
#define RST_RESET_FULL_CHIP_RESET_LSB				24
#define RST_RESET_FULL_CHIP_RESET_MASK				0x01000000
#define RST_RESET_FULL_CHIP_RESET_GET(x)			(((x) & RST_RESET_FULL_CHIP_RESET_MASK) >> RST_RESET_FULL_CHIP_RESET_LSB)
#define RST_RESET_FULL_CHIP_RESET_SET(x)			(((x) << RST_RESET_FULL_CHIP_RESET_LSB) & RST_RESET_FULL_CHIP_RESET_MASK)
#define RST_RESET_FULL_CHIP_RESET_RESET				0x0 // 0
#define RST_RESET_GE1_MDIO_RESET_MSB				23
#define RST_RESET_GE1_MDIO_RESET_LSB				23
#define RST_RESET_GE1_MDIO_RESET_MASK				0x00800000
#define RST_RESET_GE1_MDIO_RESET_GET(x)				(((x) & RST_RESET_GE1_MDIO_RESET_MASK) >> RST_RESET_GE1_MDIO_RESET_LSB)
#define RST_RESET_GE1_MDIO_RESET_SET(x)				(((x) << RST_RESET_GE1_MDIO_RESET_LSB) & RST_RESET_GE1_MDIO_RESET_MASK)
#define RST_RESET_GE1_MDIO_RESET_RESET				0x1 // 1
#define RST_RESET_GE0_MDIO_RESET_MSB				22
#define RST_RESET_GE0_MDIO_RESET_LSB				22
#define RST_RESET_GE0_MDIO_RESET_MASK				0x00400000
#define RST_RESET_GE0_MDIO_RESET_GET(x)				(((x) & RST_RESET_GE0_MDIO_RESET_MASK) >> RST_RESET_GE0_MDIO_RESET_LSB)
#define RST_RESET_GE0_MDIO_RESET_SET(x)				(((x) << RST_RESET_GE0_MDIO_RESET_LSB) & RST_RESET_GE0_MDIO_RESET_MASK)
#define RST_RESET_GE0_MDIO_RESET_RESET				0x1 // 1
#define RST_RESET_CPU_NMI_MSB					21
#define RST_RESET_CPU_NMI_LSB					21
#define RST_RESET_CPU_NMI_MASK					0x00200000
#define RST_RESET_CPU_NMI_GET(x)				(((x) & RST_RESET_CPU_NMI_MASK) >> RST_RESET_CPU_NMI_LSB)
#define RST_RESET_CPU_NMI_SET(x)				(((x) << RST_RESET_CPU_NMI_LSB) & RST_RESET_CPU_NMI_MASK)
#define RST_RESET_CPU_NMI_RESET					0x0 // 0
#define RST_RESET_CPU_COLD_RESET_MSB				20
#define RST_RESET_CPU_COLD_RESET_LSB				20
#define RST_RESET_CPU_COLD_RESET_MASK				0x00100000
#define RST_RESET_CPU_COLD_RESET_GET(x)				(((x) & RST_RESET_CPU_COLD_RESET_MASK) >> RST_RESET_CPU_COLD_RESET_LSB)
#define RST_RESET_CPU_COLD_RESET_SET(x)				(((x) << RST_RESET_CPU_COLD_RESET_LSB) & RST_RESET_CPU_COLD_RESET_MASK)
#define RST_RESET_CPU_COLD_RESET_RESET				0x0 // 0
#define RST_RESET_HOST_RESET_INT_MSB				19
#define RST_RESET_HOST_RESET_INT_LSB				19
#define RST_RESET_HOST_RESET_INT_MASK				0x00080000
#define RST_RESET_HOST_RESET_INT_GET(x)				(((x) & RST_RESET_HOST_RESET_INT_MASK) >> RST_RESET_HOST_RESET_INT_LSB)
#define RST_RESET_HOST_RESET_INT_SET(x)				(((x) << RST_RESET_HOST_RESET_INT_LSB) & RST_RESET_HOST_RESET_INT_MASK)
#define RST_RESET_HOST_RESET_INT_RESET				0x0 // 0
#define RST_RESET_PCIEEP_RESET_MSB				18
#define RST_RESET_PCIEEP_RESET_LSB				18
#define RST_RESET_PCIEEP_RESET_MASK				0x00040000
#define RST_RESET_PCIEEP_RESET_GET(x)				(((x) & RST_RESET_PCIEEP_RESET_MASK) >> RST_RESET_PCIEEP_RESET_LSB)
#define RST_RESET_PCIEEP_RESET_SET(x)				(((x) << RST_RESET_PCIEEP_RESET_LSB) & RST_RESET_PCIEEP_RESET_MASK)
#define RST_RESET_PCIEEP_RESET_RESET				0x0 // 0
#define RST_RESET_UART1_RESET_MSB				17
#define RST_RESET_UART1_RESET_LSB				17
#define RST_RESET_UART1_RESET_MASK				0x00020000
#define RST_RESET_UART1_RESET_GET(x)				(((x) & RST_RESET_UART1_RESET_MASK) >> RST_RESET_UART1_RESET_LSB)
#define RST_RESET_UART1_RESET_SET(x)				(((x) << RST_RESET_UART1_RESET_LSB) & RST_RESET_UART1_RESET_MASK)
#define RST_RESET_UART1_RESET_RESET				0x0 // 0
#define RST_RESET_DDR_RESET_MSB					16
#define RST_RESET_DDR_RESET_LSB					16
#define RST_RESET_DDR_RESET_MASK				0x00010000
#define RST_RESET_DDR_RESET_GET(x)				(((x) & RST_RESET_DDR_RESET_MASK) >> RST_RESET_DDR_RESET_LSB)
#define RST_RESET_DDR_RESET_SET(x)				(((x) << RST_RESET_DDR_RESET_LSB) & RST_RESET_DDR_RESET_MASK)
#define RST_RESET_DDR_RESET_RESET				0x0 // 0
#define RST_RESET_USB_PHY_PLL_PWD_EXT_MSB			15
#define RST_RESET_USB_PHY_PLL_PWD_EXT_LSB			15
#define RST_RESET_USB_PHY_PLL_PWD_EXT_MASK			0x00008000
#define RST_RESET_USB_PHY_PLL_PWD_EXT_GET(x)			(((x) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK) >> RST_RESET_USB_PHY_PLL_PWD_EXT_LSB)
#define RST_RESET_USB_PHY_PLL_PWD_EXT_SET(x)			(((x) << RST_RESET_USB_PHY_PLL_PWD_EXT_LSB) & RST_RESET_USB_PHY_PLL_PWD_EXT_MASK)
#define RST_RESET_USB_PHY_PLL_PWD_EXT_RESET			0x0 // 0
#define RST_RESET_NANDF_RESET_MSB				14
#define RST_RESET_NANDF_RESET_LSB				14
#define RST_RESET_NANDF_RESET_MASK				0x00004000
#define RST_RESET_NANDF_RESET_GET(x)				(((x) & RST_RESET_NANDF_RESET_MASK) >> RST_RESET_NANDF_RESET_LSB)
#define RST_RESET_NANDF_RESET_SET(x)				(((x) << RST_RESET_NANDF_RESET_LSB) & RST_RESET_NANDF_RESET_MASK)
#define RST_RESET_NANDF_RESET_RESET				0x1 // 1
#define RST_RESET_GE1_MAC_RESET_MSB				13
#define RST_RESET_GE1_MAC_RESET_LSB				13
#define RST_RESET_GE1_MAC_RESET_MASK				0x00002000
#define RST_RESET_GE1_MAC_RESET_GET(x)				(((x) & RST_RESET_GE1_MAC_RESET_MASK) >> RST_RESET_GE1_MAC_RESET_LSB)
#define RST_RESET_GE1_MAC_RESET_SET(x)				(((x) << RST_RESET_GE1_MAC_RESET_LSB) & RST_RESET_GE1_MAC_RESET_MASK)
#define RST_RESET_GE1_MAC_RESET_RESET				0x1 // 1
#define RST_RESET_ETH_SGMII_ARESET_MSB				12
#define RST_RESET_ETH_SGMII_ARESET_LSB				12
#define RST_RESET_ETH_SGMII_ARESET_MASK				0x00001000
#define RST_RESET_ETH_SGMII_ARESET_GET(x)			(((x) & RST_RESET_ETH_SGMII_ARESET_MASK) >> RST_RESET_ETH_SGMII_ARESET_LSB)
#define RST_RESET_ETH_SGMII_ARESET_SET(x)			(((x) << RST_RESET_ETH_SGMII_ARESET_LSB) & RST_RESET_ETH_SGMII_ARESET_MASK)
#define RST_RESET_ETH_SGMII_ARESET_RESET			0x1 // 1
#define RST_RESET_USB_PHY_ARESET_MSB				11
#define RST_RESET_USB_PHY_ARESET_LSB				11
#define RST_RESET_USB_PHY_ARESET_MASK				0x00000800
#define RST_RESET_USB_PHY_ARESET_GET(x)				(((x) & RST_RESET_USB_PHY_ARESET_MASK) >> RST_RESET_USB_PHY_ARESET_LSB)
#define RST_RESET_USB_PHY_ARESET_SET(x)				(((x) << RST_RESET_USB_PHY_ARESET_LSB) & RST_RESET_USB_PHY_ARESET_MASK)
#define RST_RESET_USB_PHY_ARESET_RESET				0x1 // 1
#define RST_RESET_HOST_DMA_INT_MSB				10
#define RST_RESET_HOST_DMA_INT_LSB				10
#define RST_RESET_HOST_DMA_INT_MASK				0x00000400
#define RST_RESET_HOST_DMA_INT_GET(x)				(((x) & RST_RESET_HOST_DMA_INT_MASK) >> RST_RESET_HOST_DMA_INT_LSB)
#define RST_RESET_HOST_DMA_INT_SET(x)				(((x) << RST_RESET_HOST_DMA_INT_LSB) & RST_RESET_HOST_DMA_INT_MASK)
#define RST_RESET_HOST_DMA_INT_RESET				0x0 // 0
#define RST_RESET_GE0_MAC_RESET_MSB				9
#define RST_RESET_GE0_MAC_RESET_LSB				9
#define RST_RESET_GE0_MAC_RESET_MASK				0x00000200
#define RST_RESET_GE0_MAC_RESET_GET(x)				(((x) & RST_RESET_GE0_MAC_RESET_MASK) >> RST_RESET_GE0_MAC_RESET_LSB)
#define RST_RESET_GE0_MAC_RESET_SET(x)				(((x) << RST_RESET_GE0_MAC_RESET_LSB) & RST_RESET_GE0_MAC_RESET_MASK)
#define RST_RESET_GE0_MAC_RESET_RESET				0x1 // 1
#define RST_RESET_ETH_SGMII_RESET_MSB				8
#define RST_RESET_ETH_SGMII_RESET_LSB				8
#define RST_RESET_ETH_SGMII_RESET_MASK				0x00000100
#define RST_RESET_ETH_SGMII_RESET_GET(x)			(((x) & RST_RESET_ETH_SGMII_RESET_MASK) >> RST_RESET_ETH_SGMII_RESET_LSB)
#define RST_RESET_ETH_SGMII_RESET_SET(x)			(((x) << RST_RESET_ETH_SGMII_RESET_LSB) & RST_RESET_ETH_SGMII_RESET_MASK)
#define RST_RESET_ETH_SGMII_RESET_RESET				0x1 // 1
#define RST_RESET_PCIE_PHY_RESET_MSB				7
#define RST_RESET_PCIE_PHY_RESET_LSB				7
#define RST_RESET_PCIE_PHY_RESET_MASK				0x00000080
#define RST_RESET_PCIE_PHY_RESET_GET(x)				(((x) & RST_RESET_PCIE_PHY_RESET_MASK) >> RST_RESET_PCIE_PHY_RESET_LSB)
#define RST_RESET_PCIE_PHY_RESET_SET(x)				(((x) << RST_RESET_PCIE_PHY_RESET_LSB) & RST_RESET_PCIE_PHY_RESET_MASK)
#define RST_RESET_PCIE_PHY_RESET_RESET				0x1 // 1
#define RST_RESET_PCIE_RESET_MSB				6
#define RST_RESET_PCIE_RESET_LSB				6
#define RST_RESET_PCIE_RESET_MASK				0x00000040
#define RST_RESET_PCIE_RESET_GET(x)				(((x) & RST_RESET_PCIE_RESET_MASK) >> RST_RESET_PCIE_RESET_LSB)
#define RST_RESET_PCIE_RESET_SET(x)				(((x) << RST_RESET_PCIE_RESET_LSB) & RST_RESET_PCIE_RESET_MASK)
#define RST_RESET_PCIE_RESET_RESET				0x1 // 1
#define RST_RESET_USB_HOST_RESET_MSB				5
#define RST_RESET_USB_HOST_RESET_LSB				5
#define RST_RESET_USB_HOST_RESET_MASK				0x00000020
#define RST_RESET_USB_HOST_RESET_GET(x)				(((x) & RST_RESET_USB_HOST_RESET_MASK) >> RST_RESET_USB_HOST_RESET_LSB)
#define RST_RESET_USB_HOST_RESET_SET(x)				(((x) << RST_RESET_USB_HOST_RESET_LSB) & RST_RESET_USB_HOST_RESET_MASK)
#define RST_RESET_USB_HOST_RESET_RESET				0x1 // 1
#define RST_RESET_USB_PHY_RESET_MSB				4
#define RST_RESET_USB_PHY_RESET_LSB				4
#define RST_RESET_USB_PHY_RESET_MASK				0x00000010
#define RST_RESET_USB_PHY_RESET_GET(x)				(((x) & RST_RESET_USB_PHY_RESET_MASK) >> RST_RESET_USB_PHY_RESET_LSB)
#define RST_RESET_USB_PHY_RESET_SET(x)				(((x) << RST_RESET_USB_PHY_RESET_LSB) & RST_RESET_USB_PHY_RESET_MASK)
#define RST_RESET_USB_PHY_RESET_RESET				0x1 // 1
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MSB			3
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB			3
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK			0x00000008
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_GET(x)		(((x) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK) >> RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB)
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_SET(x)		(((x) << RST_RESET_USB_PHY_SUSPEND_OVERRIDE_LSB) & RST_RESET_USB_PHY_SUSPEND_OVERRIDE_MASK)
#define RST_RESET_USB_PHY_SUSPEND_OVERRIDE_RESET		0x0 // 0
#define RST_RESET_LUT_RESET_MSB					2
#define RST_RESET_LUT_RESET_LSB					2
#define RST_RESET_LUT_RESET_MASK				0x00000004
#define RST_RESET_LUT_RESET_GET(x)				(((x) & RST_RESET_LUT_RESET_MASK) >> RST_RESET_LUT_RESET_LSB)
#define RST_RESET_LUT_RESET_SET(x)				(((x) << RST_RESET_LUT_RESET_LSB) & RST_RESET_LUT_RESET_MASK)
#define RST_RESET_LUT_RESET_RESET				0x0 // 0
#define RST_RESET_MBOX_RESET_MSB				1
#define RST_RESET_MBOX_RESET_LSB				1
#define RST_RESET_MBOX_RESET_MASK				0x00000002
#define RST_RESET_MBOX_RESET_GET(x)				(((x) & RST_RESET_MBOX_RESET_MASK) >> RST_RESET_MBOX_RESET_LSB)
#define RST_RESET_MBOX_RESET_SET(x)				(((x) << RST_RESET_MBOX_RESET_LSB) & RST_RESET_MBOX_RESET_MASK)
#define RST_RESET_MBOX_RESET_RESET				0x0 // 0
#define RST_RESET_I2S_RESET_MSB					0
#define RST_RESET_I2S_RESET_LSB					0
#define RST_RESET_I2S_RESET_MASK				0x00000001
#define RST_RESET_I2S_RESET_GET(x)				(((x) & RST_RESET_I2S_RESET_MASK) >> RST_RESET_I2S_RESET_LSB)
#define RST_RESET_I2S_RESET_SET(x)				(((x) << RST_RESET_I2S_RESET_LSB) & RST_RESET_I2S_RESET_MASK)
#define RST_RESET_I2S_RESET_RESET				0x0 // 0
#define RST_RESET_ADDRESS					0x1806001c

// 0x18060090	RST_REVISION_ID
#define RST_REVISION_ID_VALUE_MSB				31
#define RST_REVISION_ID_VALUE_LSB				0
#define RST_REVISION_ID_VALUE_MASK				0xffffffff
#define RST_REVISION_ID_VALUE_GET(x)				(((x) & RST_REVISION_ID_VALUE_MASK) >> RST_REVISION_ID_VALUE_LSB)
#define RST_REVISION_ID_VALUE_SET(x)				(((x) << RST_REVISION_ID_VALUE_LSB) & RST_REVISION_ID_VALUE_MASK)
#define RST_REVISION_ID_ADDRESS					0x18060090

// 0x180600b0	RST_BOOTSTRAP
#define RST_BOOTSTRAP_BOOT_INTF_SEL_MSB				17
#define RST_BOOTSTRAP_BOOT_INTF_SEL_LSB				16
#define RST_BOOTSTRAP_BOOT_INTF_SEL_MASK			0x00030000
#define RST_BOOTSTRAP_BOOT_INTF_SEL_GET(x)			(((x) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK) >> RST_BOOTSTRAP_BOOT_INTF_SEL_LSB)
#define RST_BOOTSTRAP_BOOT_INTF_SEL_SET(x)			(((x) << RST_BOOTSTRAP_BOOT_INTF_SEL_LSB) & RST_BOOTSTRAP_BOOT_INTF_SEL_MASK)
#define RST_BOOTSTRAP_BOOT_INTF_SEL_RESET			0x0 // 0
#define RST_BOOTSTRAP_RES0_MSB					15
#define RST_BOOTSTRAP_RES0_LSB					13
#define RST_BOOTSTRAP_RES0_MASK					0x0000e000
#define RST_BOOTSTRAP_RES0_GET(x)				(((x) & RST_BOOTSTRAP_RES0_MASK) >> RST_BOOTSTRAP_RES0_LSB)
#define RST_BOOTSTRAP_RES0_SET(x)				(((x) << RST_BOOTSTRAP_RES0_LSB) & RST_BOOTSTRAP_RES0_MASK)
#define RST_BOOTSTRAP_RES0_RESET				0x0 // 0
#define RST_BOOTSTRAP_SW_OPTION2_MSB				12
#define RST_BOOTSTRAP_SW_OPTION2_LSB				12
#define RST_BOOTSTRAP_SW_OPTION2_MASK				0x00001000
#define RST_BOOTSTRAP_SW_OPTION2_GET(x)				(((x) & RST_BOOTSTRAP_SW_OPTION2_MASK) >> RST_BOOTSTRAP_SW_OPTION2_LSB)
#define RST_BOOTSTRAP_SW_OPTION2_SET(x)				(((x) << RST_BOOTSTRAP_SW_OPTION2_LSB) & RST_BOOTSTRAP_SW_OPTION2_MASK)
#define RST_BOOTSTRAP_SW_OPTION2_RESET				0x0 // 0
#define RST_BOOTSTRAP_SW_OPTION1_MSB				11
#define RST_BOOTSTRAP_SW_OPTION1_LSB				11
#define RST_BOOTSTRAP_SW_OPTION1_MASK				0x00000800
#define RST_BOOTSTRAP_SW_OPTION1_GET(x)				(((x) & RST_BOOTSTRAP_SW_OPTION1_MASK) >> RST_BOOTSTRAP_SW_OPTION1_LSB)
#define RST_BOOTSTRAP_SW_OPTION1_SET(x)				(((x) << RST_BOOTSTRAP_SW_OPTION1_LSB) & RST_BOOTSTRAP_SW_OPTION1_MASK)
#define RST_BOOTSTRAP_SW_OPTION1_RESET				0x0 // 0
#define RST_BOOTSTRAP_TESTROM_DISABLE_MSB			10
#define RST_BOOTSTRAP_TESTROM_DISABLE_LSB			10
#define RST_BOOTSTRAP_TESTROM_DISABLE_MASK			0x00000400
#define RST_BOOTSTRAP_TESTROM_DISABLE_GET(x)			(((x) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK) >> RST_BOOTSTRAP_TESTROM_DISABLE_LSB)
#define RST_BOOTSTRAP_TESTROM_DISABLE_SET(x)			(((x) << RST_BOOTSTRAP_TESTROM_DISABLE_LSB) & RST_BOOTSTRAP_TESTROM_DISABLE_MASK)
#define RST_BOOTSTRAP_TESTROM_DISABLE_RESET			0x1 // 1
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MSB			9
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB			9
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK		0x00000200
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_GET(x)		(((x) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK) >> RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB)
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_SET(x)		(((x) << RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_LSB) & RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_MASK)
#define RST_BOOTSTRAP_DISABLE_OTPMEM_ACCESS_RESET		0x0 // 0
#define RST_BOOTSTRAP_SRIF_ENABLE_MSB				8
#define RST_BOOTSTRAP_SRIF_ENABLE_LSB				8
#define RST_BOOTSTRAP_SRIF_ENABLE_MASK				0x00000100
#define RST_BOOTSTRAP_SRIF_ENABLE_GET(x)			(((x) & RST_BOOTSTRAP_SRIF_ENABLE_MASK) >> RST_BOOTSTRAP_SRIF_ENABLE_LSB)
#define RST_BOOTSTRAP_SRIF_ENABLE_SET(x)			(((x) << RST_BOOTSTRAP_SRIF_ENABLE_LSB) & RST_BOOTSTRAP_SRIF_ENABLE_MASK)
#define RST_BOOTSTRAP_SRIF_ENABLE_RESET				0x0 // 0
#define RST_BOOTSTRAP_USB_MODE_MSB				7
#define RST_BOOTSTRAP_USB_MODE_LSB				7
#define RST_BOOTSTRAP_USB_MODE_MASK				0x00000080
#define RST_BOOTSTRAP_USB_MODE_GET(x)				(((x) & RST_BOOTSTRAP_USB_MODE_MASK) >> RST_BOOTSTRAP_USB_MODE_LSB)
#define RST_BOOTSTRAP_USB_MODE_SET(x)				(((x) << RST_BOOTSTRAP_USB_MODE_LSB) & RST_BOOTSTRAP_USB_MODE_MASK)
#define RST_BOOTSTRAP_USB_MODE_RESET				0x0 // 0
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MSB			6
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB			6
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK			0x00000040
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_GET(x)			(((x) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK) >> RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB)
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_SET(x)			(((x) << RST_BOOTSTRAP_PCIE_RC_EP_SELECT_LSB) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)
#define RST_BOOTSTRAP_PCIE_RC_EP_SELECT_RESET			0x0 // 0
#define RST_BOOTSTRAP_JTAG_MODE_MSB				5
#define RST_BOOTSTRAP_JTAG_MODE_LSB				5
#define RST_BOOTSTRAP_JTAG_MODE_MASK				0x00000020
#define RST_BOOTSTRAP_JTAG_MODE_GET(x)				(((x) & RST_BOOTSTRAP_JTAG_MODE_MASK) >> RST_BOOTSTRAP_JTAG_MODE_LSB)
#define RST_BOOTSTRAP_JTAG_MODE_SET(x)				(((x) << RST_BOOTSTRAP_JTAG_MODE_LSB) & RST_BOOTSTRAP_JTAG_MODE_MASK)
#define RST_BOOTSTRAP_JTAG_MODE_RESET				0x1 // 1
#define RST_BOOTSTRAP_REF_CLK_MSB				4
#define RST_BOOTSTRAP_REF_CLK_LSB				4
#define RST_BOOTSTRAP_REF_CLK_MASK				0x00000010
#define RST_BOOTSTRAP_REF_CLK_GET(x)				(((x) & RST_BOOTSTRAP_REF_CLK_MASK) >> RST_BOOTSTRAP_REF_CLK_LSB)
#define RST_BOOTSTRAP_REF_CLK_SET(x)				(((x) << RST_BOOTSTRAP_REF_CLK_LSB) & RST_BOOTSTRAP_REF_CLK_MASK)
#define RST_BOOTSTRAP_REF_CLK_RESET				0x0 // 0
#define RST_BOOTSTRAP_DDR_WIDTH_MSB				3
#define RST_BOOTSTRAP_DDR_WIDTH_LSB				3
#define RST_BOOTSTRAP_DDR_WIDTH_MASK				0x00000008
#define RST_BOOTSTRAP_DDR_WIDTH_GET(x)				(((x) & RST_BOOTSTRAP_DDR_WIDTH_MASK) >> RST_BOOTSTRAP_DDR_WIDTH_LSB)
#define RST_BOOTSTRAP_DDR_WIDTH_SET(x)				(((x) << RST_BOOTSTRAP_DDR_WIDTH_LSB) & RST_BOOTSTRAP_DDR_WIDTH_MASK)
#define RST_BOOTSTRAP_DDR_WIDTH_RESET				0x0 // 0
#define RST_BOOTSTRAP_BOOT_SELECT_MSB				2
#define RST_BOOTSTRAP_BOOT_SELECT_LSB				2
#define RST_BOOTSTRAP_BOOT_SELECT_MASK				0x00000004
#define RST_BOOTSTRAP_BOOT_SELECT_GET(x)			(((x) & RST_BOOTSTRAP_BOOT_SELECT_MASK) >> RST_BOOTSTRAP_BOOT_SELECT_LSB)
#define RST_BOOTSTRAP_BOOT_SELECT_SET(x)			(((x) << RST_BOOTSTRAP_BOOT_SELECT_LSB) & RST_BOOTSTRAP_BOOT_SELECT_MASK)
#define RST_BOOTSTRAP_BOOT_SELECT_RESET				0x0 // 0
#define RST_BOOTSTRAP_SDRAM_DISABLE_MSB				1
#define RST_BOOTSTRAP_SDRAM_DISABLE_LSB				1
#define RST_BOOTSTRAP_SDRAM_DISABLE_MASK			0x00000002
#define RST_BOOTSTRAP_SDRAM_DISABLE_GET(x)			(((x) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK) >> RST_BOOTSTRAP_SDRAM_DISABLE_LSB)
#define RST_BOOTSTRAP_SDRAM_DISABLE_SET(x)			(((x) << RST_BOOTSTRAP_SDRAM_DISABLE_LSB) & RST_BOOTSTRAP_SDRAM_DISABLE_MASK)
#define RST_BOOTSTRAP_SDRAM_DISABLE_RESET			0x0 // 0
#define RST_BOOTSTRAP_DDR_SELECT_MSB				0
#define RST_BOOTSTRAP_DDR_SELECT_LSB				0
#define RST_BOOTSTRAP_DDR_SELECT_MASK				0x00000001
#define RST_BOOTSTRAP_DDR_SELECT_GET(x)				(((x) & RST_BOOTSTRAP_DDR_SELECT_MASK) >> RST_BOOTSTRAP_DDR_SELECT_LSB)
#define RST_BOOTSTRAP_DDR_SELECT_SET(x)				(((x) << RST_BOOTSTRAP_DDR_SELECT_LSB) & RST_BOOTSTRAP_DDR_SELECT_MASK)
#define RST_BOOTSTRAP_DDR_SELECT_RESET				0x0 // 0
#define RST_BOOTSTRAP_ADDRESS					0x180600b0

// 0x180600b4	OTP_INTF
#define OTP_INTF_BOND_OPTION_MSB				31
#define OTP_INTF_BOND_OPTION_LSB				0
#define OTP_INTF_BOND_OPTION_MASK				0xffffffff
#define OTP_INTF_BOND_OPTION_GET(x)				(((x) & OTP_INTF_BOND_OPTION_MASK) >> OTP_INTF_BOND_OPTION_LSB)
#define OTP_INTF_BOND_OPTION_SET(x)				(((x) << OTP_INTF_BOND_OPTION_LSB) & OTP_INTF_BOND_OPTION_MASK)
#define OTP_INTF_BOND_OPTION_RESET				0x0 // 0
#define OTP_INTF_ADDRESS					0x180600b4

// 0x180600bc	RST_MISC2
#define RST_MISC2_PCIEEP_LINK_UP_MSB				30
#define RST_MISC2_PCIEEP_LINK_UP_LSB				30
#define RST_MISC2_PCIEEP_LINK_UP_MASK				0x40000000
#define RST_MISC2_PCIEEP_LINK_UP_GET(x)				(((x) & RST_MISC2_PCIEEP_LINK_UP_MASK) >> RST_MISC2_PCIEEP_LINK_UP_LSB)
#define RST_MISC2_PCIEEP_LINK_UP_SET(x)				(((x) << RST_MISC2_PCIEEP_LINK_UP_LSB) & RST_MISC2_PCIEEP_LINK_UP_MASK)
#define RST_MISC2_PCIEEP_LINK_UP_RESET				0x0 // 0
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MSB			29
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB			29
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK			0x20000000
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_GET(x)			(((x) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK) >> RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB)
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_SET(x)			(((x) << RST_MISC2_PCIEEP_CLKOBS2_SEL_LSB) & RST_MISC2_PCIEEP_CLKOBS2_SEL_MASK)
#define RST_MISC2_PCIEEP_CLKOBS2_SEL_RESET			0x0 // 0
#define RST_MISC2_PCIE_CLKOBS1_SEL_MSB				28
#define RST_MISC2_PCIE_CLKOBS1_SEL_LSB				28
#define RST_MISC2_PCIE_CLKOBS1_SEL_MASK				0x10000000
#define RST_MISC2_PCIE_CLKOBS1_SEL_GET(x)			(((x) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK) >> RST_MISC2_PCIE_CLKOBS1_SEL_LSB)
#define RST_MISC2_PCIE_CLKOBS1_SEL_SET(x)			(((x) << RST_MISC2_PCIE_CLKOBS1_SEL_LSB) & RST_MISC2_PCIE_CLKOBS1_SEL_MASK)
#define RST_MISC2_PCIE_CLKOBS1_SEL_RESET			0x0 // 0
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MSB		27
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB		27
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK		0x08000000
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_GET(x)		(((x) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK) >> RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB)
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_SET(x)		(((x) << RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_LSB) & RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_MASK)
#define RST_MISC2_JTAG_EJTAG_SWITCH_CPU_CTRL_RESET		0x0 // 0
#define RST_MISC2_WOW_STATUS_MSB				26
#define RST_MISC2_WOW_STATUS_LSB				26
#define RST_MISC2_WOW_STATUS_MASK				0x04000000
#define RST_MISC2_WOW_STATUS_GET(x)				(((x) & RST_MISC2_WOW_STATUS_MASK) >> RST_MISC2_WOW_STATUS_LSB)
#define RST_MISC2_WOW_STATUS_SET(x)				(((x) << RST_MISC2_WOW_STATUS_LSB) & RST_MISC2_WOW_STATUS_MASK)
#define RST_MISC2_WOW_STATUS_RESET				0x0 // 0
#define RST_MISC2_PCIEEP_L2_EXIT_INT_MSB			25
#define RST_MISC2_PCIEEP_L2_EXIT_INT_LSB			25
#define RST_MISC2_PCIEEP_L2_EXIT_INT_MASK			0x02000000
#define RST_MISC2_PCIEEP_L2_EXIT_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L2_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L2_EXIT_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L2_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L2_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L2_EXIT_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_L2_ENTR_INT_MSB			24
#define RST_MISC2_PCIEEP_L2_ENTR_INT_LSB			24
#define RST_MISC2_PCIEEP_L2_ENTR_INT_MASK			0x01000000
#define RST_MISC2_PCIEEP_L2_ENTR_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L2_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L2_ENTR_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L2_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L2_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L2_ENTR_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_L1_EXIT_INT_MSB			23
#define RST_MISC2_PCIEEP_L1_EXIT_INT_LSB			23
#define RST_MISC2_PCIEEP_L1_EXIT_INT_MASK			0x00800000
#define RST_MISC2_PCIEEP_L1_EXIT_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L1_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L1_EXIT_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L1_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L1_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L1_EXIT_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_L1_ENTR_INT_MSB			22
#define RST_MISC2_PCIEEP_L1_ENTR_INT_LSB			22
#define RST_MISC2_PCIEEP_L1_ENTR_INT_MASK			0x00400000
#define RST_MISC2_PCIEEP_L1_ENTR_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L1_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L1_ENTR_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L1_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L1_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L1_ENTR_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MSB			21
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB			21
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK			0x00200000
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK) >> RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB)
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L0S_EXIT_INT_LSB) & RST_MISC2_PCIEEP_L0S_EXIT_INT_MASK)
#define RST_MISC2_PCIEEP_L0S_EXIT_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MSB			20
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB			20
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK			0x00100000
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_GET(x)			(((x) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK) >> RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB)
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_SET(x)			(((x) << RST_MISC2_PCIEEP_L0S_ENTR_INT_LSB) & RST_MISC2_PCIEEP_L0S_ENTR_INT_MASK)
#define RST_MISC2_PCIEEP_L0S_ENTR_INT_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_REGWR_EN_MSB				19
#define RST_MISC2_PCIEEP_REGWR_EN_LSB				19
#define RST_MISC2_PCIEEP_REGWR_EN_MASK				0x00080000
#define RST_MISC2_PCIEEP_REGWR_EN_GET(x)			(((x) & RST_MISC2_PCIEEP_REGWR_EN_MASK) >> RST_MISC2_PCIEEP_REGWR_EN_LSB)
#define RST_MISC2_PCIEEP_REGWR_EN_SET(x)			(((x) << RST_MISC2_PCIEEP_REGWR_EN_LSB) & RST_MISC2_PCIEEP_REGWR_EN_MASK)
#define RST_MISC2_PCIEEP_REGWR_EN_RESET				0x1 // 1
#define RST_MISC2_EXT_HOST_WASP_RST_EN_MSB			18
#define RST_MISC2_EXT_HOST_WASP_RST_EN_LSB			18
#define RST_MISC2_EXT_HOST_WASP_RST_EN_MASK			0x00040000
#define RST_MISC2_EXT_HOST_WASP_RST_EN_GET(x)			(((x) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK) >> RST_MISC2_EXT_HOST_WASP_RST_EN_LSB)
#define RST_MISC2_EXT_HOST_WASP_RST_EN_SET(x)			(((x) << RST_MISC2_EXT_HOST_WASP_RST_EN_LSB) & RST_MISC2_EXT_HOST_WASP_RST_EN_MASK)
#define RST_MISC2_EXT_HOST_WASP_RST_EN_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_RST_INT_MSB				17
#define RST_MISC2_PCIEEP_RST_INT_LSB				17
#define RST_MISC2_PCIEEP_RST_INT_MASK				0x00020000
#define RST_MISC2_PCIEEP_RST_INT_GET(x)				(((x) & RST_MISC2_PCIEEP_RST_INT_MASK) >> RST_MISC2_PCIEEP_RST_INT_LSB)
#define RST_MISC2_PCIEEP_RST_INT_SET(x)				(((x) << RST_MISC2_PCIEEP_RST_INT_LSB) & RST_MISC2_PCIEEP_RST_INT_MASK)
#define RST_MISC2_PCIEEP_RST_INT_RESET				0x0 // 0
#define RST_MISC2_HOST_RESET_INT_MSB				16
#define RST_MISC2_HOST_RESET_INT_LSB				16
#define RST_MISC2_HOST_RESET_INT_MASK				0x00010000
#define RST_MISC2_HOST_RESET_INT_GET(x)				(((x) & RST_MISC2_HOST_RESET_INT_MASK) >> RST_MISC2_HOST_RESET_INT_LSB)
#define RST_MISC2_HOST_RESET_INT_SET(x)				(((x) << RST_MISC2_HOST_RESET_INT_LSB) & RST_MISC2_HOST_RESET_INT_MASK)
#define RST_MISC2_HOST_RESET_INT_RESET				0x0 // 0
#define RST_MISC2_CPU_HOST_WA_MSB				15
#define RST_MISC2_CPU_HOST_WA_LSB				15
#define RST_MISC2_CPU_HOST_WA_MASK				0x00008000
#define RST_MISC2_CPU_HOST_WA_GET(x)				(((x) & RST_MISC2_CPU_HOST_WA_MASK) >> RST_MISC2_CPU_HOST_WA_LSB)
#define RST_MISC2_CPU_HOST_WA_SET(x)				(((x) << RST_MISC2_CPU_HOST_WA_LSB) & RST_MISC2_CPU_HOST_WA_MASK)
#define RST_MISC2_CPU_HOST_WA_RESET				0x0 // 0
#define RST_MISC2_PERSTN_RCPHY2_MSB				14
#define RST_MISC2_PERSTN_RCPHY2_LSB				14
#define RST_MISC2_PERSTN_RCPHY2_MASK				0x00004000
#define RST_MISC2_PERSTN_RCPHY2_GET(x)				(((x) & RST_MISC2_PERSTN_RCPHY2_MASK) >> RST_MISC2_PERSTN_RCPHY2_LSB)
#define RST_MISC2_PERSTN_RCPHY2_SET(x)				(((x) << RST_MISC2_PERSTN_RCPHY2_LSB) & RST_MISC2_PERSTN_RCPHY2_MASK)
#define RST_MISC2_PERSTN_RCPHY2_RESET				0x1 // 1
#define RST_MISC2_PERSTN_RCPHY_MSB				13
#define RST_MISC2_PERSTN_RCPHY_LSB				13
#define RST_MISC2_PERSTN_RCPHY_MASK				0x00002000
#define RST_MISC2_PERSTN_RCPHY_GET(x)				(((x) & RST_MISC2_PERSTN_RCPHY_MASK) >> RST_MISC2_PERSTN_RCPHY_LSB)
#define RST_MISC2_PERSTN_RCPHY_SET(x)				(((x) << RST_MISC2_PERSTN_RCPHY_LSB) & RST_MISC2_PERSTN_RCPHY_MASK)
#define RST_MISC2_PERSTN_RCPHY_RESET				0x1 // 1
#define RST_MISC2_PCIEEP_LTSSM_STATE_MSB			12
#define RST_MISC2_PCIEEP_LTSSM_STATE_LSB			8
#define RST_MISC2_PCIEEP_LTSSM_STATE_MASK			0x00001f00
#define RST_MISC2_PCIEEP_LTSSM_STATE_GET(x)			(((x) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK) >> RST_MISC2_PCIEEP_LTSSM_STATE_LSB)
#define RST_MISC2_PCIEEP_LTSSM_STATE_SET(x)			(((x) << RST_MISC2_PCIEEP_LTSSM_STATE_LSB) & RST_MISC2_PCIEEP_LTSSM_STATE_MASK)
#define RST_MISC2_PCIEEP_LTSSM_STATE_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_LINK_STATUS_MSB			4
#define RST_MISC2_PCIEEP_LINK_STATUS_LSB			4
#define RST_MISC2_PCIEEP_LINK_STATUS_MASK			0x00000010
#define RST_MISC2_PCIEEP_LINK_STATUS_GET(x)			(((x) & RST_MISC2_PCIEEP_LINK_STATUS_MASK) >> RST_MISC2_PCIEEP_LINK_STATUS_LSB)
#define RST_MISC2_PCIEEP_LINK_STATUS_SET(x)			(((x) << RST_MISC2_PCIEEP_LINK_STATUS_LSB) & RST_MISC2_PCIEEP_LINK_STATUS_MASK)
#define RST_MISC2_PCIEEP_LINK_STATUS_RESET			0x0 // 0
#define RST_MISC2_WOW_DETECT_MSB				3
#define RST_MISC2_WOW_DETECT_LSB				3
#define RST_MISC2_WOW_DETECT_MASK				0x00000008
#define RST_MISC2_WOW_DETECT_GET(x)				(((x) & RST_MISC2_WOW_DETECT_MASK) >> RST_MISC2_WOW_DETECT_LSB)
#define RST_MISC2_WOW_DETECT_SET(x)				(((x) << RST_MISC2_WOW_DETECT_LSB) & RST_MISC2_WOW_DETECT_MASK)
#define RST_MISC2_WOW_DETECT_RESET				0x0 // 0
#define RST_MISC2_PCIEEP_RXDETECT_DONE_MSB			2
#define RST_MISC2_PCIEEP_RXDETECT_DONE_LSB			2
#define RST_MISC2_PCIEEP_RXDETECT_DONE_MASK			0x00000004
#define RST_MISC2_PCIEEP_RXDETECT_DONE_GET(x)			(((x) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK) >> RST_MISC2_PCIEEP_RXDETECT_DONE_LSB)
#define RST_MISC2_PCIEEP_RXDETECT_DONE_SET(x)			(((x) << RST_MISC2_PCIEEP_RXDETECT_DONE_LSB) & RST_MISC2_PCIEEP_RXDETECT_DONE_MASK)
#define RST_MISC2_PCIEEP_RXDETECT_DONE_RESET			0x0 // 0
#define RST_MISC2_PCIEEP_WOW_INT_MSB				1
#define RST_MISC2_PCIEEP_WOW_INT_LSB				1
#define RST_MISC2_PCIEEP_WOW_INT_MASK				0x00000002
#define RST_MISC2_PCIEEP_WOW_INT_GET(x)				(((x) & RST_MISC2_PCIEEP_WOW_INT_MASK) >> RST_MISC2_PCIEEP_WOW_INT_LSB)
#define RST_MISC2_PCIEEP_WOW_INT_SET(x)				(((x) << RST_MISC2_PCIEEP_WOW_INT_LSB) & RST_MISC2_PCIEEP_WOW_INT_MASK)
#define RST_MISC2_PCIEEP_WOW_INT_RESET				0x0 // 0
#define RST_MISC2_PCIEEP_CFG_DONE_MSB				0
#define RST_MISC2_PCIEEP_CFG_DONE_LSB				0
#define RST_MISC2_PCIEEP_CFG_DONE_MASK				0x00000001
#define RST_MISC2_PCIEEP_CFG_DONE_GET(x)			(((x) & RST_MISC2_PCIEEP_CFG_DONE_MASK) >> RST_MISC2_PCIEEP_CFG_DONE_LSB)
#define RST_MISC2_PCIEEP_CFG_DONE_SET(x)			(((x) << RST_MISC2_PCIEEP_CFG_DONE_LSB) & RST_MISC2_PCIEEP_CFG_DONE_MASK)
#define RST_MISC2_PCIEEP_CFG_DONE_RESET				0x0 // 0
#define RST_MISC2_ADDRESS					0x180600bc

// 0x180600c4	RST_RESET2
#define RST_RESET2_SPARE_MSB					31
#define RST_RESET2_SPARE_LSB					19
#define RST_RESET2_SPARE_MASK					0xfff80000
#define RST_RESET2_SPARE_GET(x)					(((x) & RST_RESET2_SPARE_MASK) >> RST_RESET2_SPARE_LSB)
#define RST_RESET2_SPARE_SET(x)					(((x) << RST_RESET2_SPARE_LSB) & RST_RESET2_SPARE_MASK)
#define RST_RESET2_SPARE_RESET					0x0 // 0
#define RST_RESET2_EP_MODE_MSB					18
#define RST_RESET2_EP_MODE_LSB					18
#define RST_RESET2_EP_MODE_MASK					0x00040000
#define RST_RESET2_EP_MODE_GET(x)				(((x) & RST_RESET2_EP_MODE_MASK) >> RST_RESET2_EP_MODE_LSB)
#define RST_RESET2_EP_MODE_SET(x)				(((x) << RST_RESET2_EP_MODE_LSB) & RST_RESET2_EP_MODE_MASK)
#define RST_RESET2_EP_MODE_RESET				0x0 // 0
#define RST_RESET2_USB2_EXT_PWR_SEQ_MSB				17
#define RST_RESET2_USB2_EXT_PWR_SEQ_LSB				17
#define RST_RESET2_USB2_EXT_PWR_SEQ_MASK			0x00020000
#define RST_RESET2_USB2_EXT_PWR_SEQ_GET(x)			(((x) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB2_EXT_PWR_SEQ_LSB)
#define RST_RESET2_USB2_EXT_PWR_SEQ_SET(x)			(((x) << RST_RESET2_USB2_EXT_PWR_SEQ_LSB) & RST_RESET2_USB2_EXT_PWR_SEQ_MASK)
#define RST_RESET2_USB2_EXT_PWR_SEQ_RESET			0x1 // 1
#define RST_RESET2_USB1_EXT_PWR_SEQ_MSB				16
#define RST_RESET2_USB1_EXT_PWR_SEQ_LSB				16
#define RST_RESET2_USB1_EXT_PWR_SEQ_MASK			0x00010000
#define RST_RESET2_USB1_EXT_PWR_SEQ_GET(x)			(((x) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK) >> RST_RESET2_USB1_EXT_PWR_SEQ_LSB)
#define RST_RESET2_USB1_EXT_PWR_SEQ_SET(x)			(((x) << RST_RESET2_USB1_EXT_PWR_SEQ_LSB) & RST_RESET2_USB1_EXT_PWR_SEQ_MASK)
#define RST_RESET2_USB1_EXT_PWR_SEQ_RESET			0x1 // 1
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MSB			15
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB			15
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK			0x00008000
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_GET(x)			(((x) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK) >> RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB)
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_SET(x)			(((x) << RST_RESET2_USB_PHY2_PLL_PWD_EXT_LSB) & RST_RESET2_USB_PHY2_PLL_PWD_EXT_MASK)
#define RST_RESET2_USB_PHY2_PLL_PWD_EXT_RESET			0x0 // 0
#define RST_RESET2_USB_PHY2_ARESET_MSB				11
#define RST_RESET2_USB_PHY2_ARESET_LSB				11
#define RST_RESET2_USB_PHY2_ARESET_MASK				0x00000800
#define RST_RESET2_USB_PHY2_ARESET_GET(x)			(((x) & RST_RESET2_USB_PHY2_ARESET_MASK) >> RST_RESET2_USB_PHY2_ARESET_LSB)
#define RST_RESET2_USB_PHY2_ARESET_SET(x)			(((x) << RST_RESET2_USB_PHY2_ARESET_LSB) & RST_RESET2_USB_PHY2_ARESET_MASK)
#define RST_RESET2_USB_PHY2_ARESET_RESET			0x1 // 1
#define RST_RESET2_PCIE2_PHY_RESET_MSB				7
#define RST_RESET2_PCIE2_PHY_RESET_LSB				7
#define RST_RESET2_PCIE2_PHY_RESET_MASK				0x00000080
#define RST_RESET2_PCIE2_PHY_RESET_GET(x)			(((x) & RST_RESET2_PCIE2_PHY_RESET_MASK) >> RST_RESET2_PCIE2_PHY_RESET_LSB)
#define RST_RESET2_PCIE2_PHY_RESET_SET(x)			(((x) << RST_RESET2_PCIE2_PHY_RESET_LSB) & RST_RESET2_PCIE2_PHY_RESET_MASK)
#define RST_RESET2_PCIE2_PHY_RESET_RESET			0x1 // 1
#define RST_RESET2_PCIE2_RESET_MSB				6
#define RST_RESET2_PCIE2_RESET_LSB				6
#define RST_RESET2_PCIE2_RESET_MASK				0x00000040
#define RST_RESET2_PCIE2_RESET_GET(x)				(((x) & RST_RESET2_PCIE2_RESET_MASK) >> RST_RESET2_PCIE2_RESET_LSB)
#define RST_RESET2_PCIE2_RESET_SET(x)				(((x) << RST_RESET2_PCIE2_RESET_LSB) & RST_RESET2_PCIE2_RESET_MASK)
#define RST_RESET2_PCIE2_RESET_RESET				0x1 // 1
#define RST_RESET2_USB_HOST2_RESET_MSB				5
#define RST_RESET2_USB_HOST2_RESET_LSB				5
#define RST_RESET2_USB_HOST2_RESET_MASK				0x00000020
#define RST_RESET2_USB_HOST2_RESET_GET(x)			(((x) & RST_RESET2_USB_HOST2_RESET_MASK) >> RST_RESET2_USB_HOST2_RESET_LSB)
#define RST_RESET2_USB_HOST2_RESET_SET(x)			(((x) << RST_RESET2_USB_HOST2_RESET_LSB) & RST_RESET2_USB_HOST2_RESET_MASK)
#define RST_RESET2_USB_HOST2_RESET_RESET			0x1 // 1
#define RST_RESET2_USB_PHY2_RESET_MSB				4
#define RST_RESET2_USB_PHY2_RESET_LSB				4
#define RST_RESET2_USB_PHY2_RESET_MASK				0x00000010
#define RST_RESET2_USB_PHY2_RESET_GET(x)			(((x) & RST_RESET2_USB_PHY2_RESET_MASK) >> RST_RESET2_USB_PHY2_RESET_LSB)
#define RST_RESET2_USB_PHY2_RESET_SET(x)			(((x) << RST_RESET2_USB_PHY2_RESET_LSB) & RST_RESET2_USB_PHY2_RESET_MASK)
#define RST_RESET2_USB_PHY2_RESET_RESET				0x1 // 1
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MSB		3
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB		3
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK		0x00000008
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_GET(x)		(((x) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK) >> RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB)
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_SET(x)		(((x) << RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_LSB) & RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_MASK)
#define RST_RESET2_USB_PHY2_SUSPEND_OVERRIDE_RESET		0x0 // 0
#define RST_RESET2_USB2_MODE_MSB				0
#define RST_RESET2_USB2_MODE_LSB				0
#define RST_RESET2_USB2_MODE_MASK				0x00000001
#define RST_RESET2_USB2_MODE_GET(x)				(((x) & RST_RESET2_USB2_MODE_MASK) >> RST_RESET2_USB2_MODE_LSB)
#define RST_RESET2_USB2_MODE_SET(x)				(((x) << RST_RESET2_USB2_MODE_LSB) & RST_RESET2_USB2_MODE_MASK)
#define RST_RESET2_USB2_MODE_RESET				0x1 // 1
#define RST_RESET2_ADDRESS					0x180600c4

// 0x18070000	ETH_CFG
#define ETH_CFG_ETH_SPARE_MSB					31
#define ETH_CFG_ETH_SPARE_LSB					22
#define ETH_CFG_ETH_SPARE_MASK					0xffc00000
#define ETH_CFG_ETH_SPARE_GET(x)				(((x) & ETH_CFG_ETH_SPARE_MASK) >> ETH_CFG_ETH_SPARE_LSB)
#define ETH_CFG_ETH_SPARE_SET(x)				(((x) << ETH_CFG_ETH_SPARE_LSB) & ETH_CFG_ETH_SPARE_MASK)
#define ETH_CFG_ETH_SPARE_RESET					0x0 // 0
#define ETH_CFG_ETH_TXEN_DELAY_MSB				21
#define ETH_CFG_ETH_TXEN_DELAY_LSB				20
#define ETH_CFG_ETH_TXEN_DELAY_MASK				0x00300000
#define ETH_CFG_ETH_TXEN_DELAY_GET(x)				(((x) & ETH_CFG_ETH_TXEN_DELAY_MASK) >> ETH_CFG_ETH_TXEN_DELAY_LSB)
#define ETH_CFG_ETH_TXEN_DELAY_SET(x)				(((x) << ETH_CFG_ETH_TXEN_DELAY_LSB) & ETH_CFG_ETH_TXEN_DELAY_MASK)
#define ETH_CFG_ETH_TXEN_DELAY_RESET				0x0 // 0
#define ETH_CFG_ETH_TXD_DELAY_MSB				19
#define ETH_CFG_ETH_TXD_DELAY_LSB				18
#define ETH_CFG_ETH_TXD_DELAY_MASK				0x000c0000
#define ETH_CFG_ETH_TXD_DELAY_GET(x)				(((x) & ETH_CFG_ETH_TXD_DELAY_MASK) >> ETH_CFG_ETH_TXD_DELAY_LSB)
#define ETH_CFG_ETH_TXD_DELAY_SET(x)				(((x) << ETH_CFG_ETH_TXD_DELAY_LSB) & ETH_CFG_ETH_TXD_DELAY_MASK)
#define ETH_CFG_ETH_TXD_DELAY_RESET				0x0 // 0
#define ETH_CFG_ETH_RXDV_DELAY_MSB				17
#define ETH_CFG_ETH_RXDV_DELAY_LSB				16
#define ETH_CFG_ETH_RXDV_DELAY_MASK				0x00030000
#define ETH_CFG_ETH_RXDV_DELAY_GET(x)				(((x) & ETH_CFG_ETH_RXDV_DELAY_MASK) >> ETH_CFG_ETH_RXDV_DELAY_LSB)
#define ETH_CFG_ETH_RXDV_DELAY_SET(x)				(((x) << ETH_CFG_ETH_RXDV_DELAY_LSB) & ETH_CFG_ETH_RXDV_DELAY_MASK)
#define ETH_CFG_ETH_RXDV_DELAY_RESET				0x0 // 0
#define ETH_CFG_ETH_RXD_DELAY_MSB				15
#define ETH_CFG_ETH_RXD_DELAY_LSB				14
#define ETH_CFG_ETH_RXD_DELAY_MASK				0x0000c000
#define ETH_CFG_ETH_RXD_DELAY_GET(x)				(((x) & ETH_CFG_ETH_RXD_DELAY_MASK) >> ETH_CFG_ETH_RXD_DELAY_LSB)
#define ETH_CFG_ETH_RXD_DELAY_SET(x)				(((x) << ETH_CFG_ETH_RXD_DELAY_LSB) & ETH_CFG_ETH_RXD_DELAY_MASK)
#define ETH_CFG_ETH_RXD_DELAY_RESET				0x0 // 0
#define ETH_CFG_RMII_GE0_MASTER_MSB				12
#define ETH_CFG_RMII_GE0_MASTER_LSB				12
#define ETH_CFG_RMII_GE0_MASTER_MASK				0x00001000
#define ETH_CFG_RMII_GE0_MASTER_GET(x)				(((x) & ETH_CFG_RMII_GE0_MASTER_MASK) >> ETH_CFG_RMII_GE0_MASTER_LSB)
#define ETH_CFG_RMII_GE0_MASTER_SET(x)				(((x) << ETH_CFG_RMII_GE0_MASTER_LSB) & ETH_CFG_RMII_GE0_MASTER_MASK)
#define ETH_CFG_RMII_GE0_MASTER_RESET				0x1 // 1
#define ETH_CFG_MII_CNTL_SPEED_MSB				11
#define ETH_CFG_MII_CNTL_SPEED_LSB				11
#define ETH_CFG_MII_CNTL_SPEED_MASK				0x00000800
#define ETH_CFG_MII_CNTL_SPEED_GET(x)				(((x) & ETH_CFG_MII_CNTL_SPEED_MASK) >> ETH_CFG_MII_CNTL_SPEED_LSB)
#define ETH_CFG_MII_CNTL_SPEED_SET(x)				(((x) << ETH_CFG_MII_CNTL_SPEED_LSB) & ETH_CFG_MII_CNTL_SPEED_MASK)
#define ETH_CFG_MII_CNTL_SPEED_RESET				0x0 // 0
#define ETH_CFG_RMII_GE0_MSB					10
#define ETH_CFG_RMII_GE0_LSB					10
#define ETH_CFG_RMII_GE0_MASK					0x00000400
#define ETH_CFG_RMII_GE0_GET(x)					(((x) & ETH_CFG_RMII_GE0_MASK) >> ETH_CFG_RMII_GE0_LSB)
#define ETH_CFG_RMII_GE0_SET(x)					(((x) << ETH_CFG_RMII_GE0_LSB) & ETH_CFG_RMII_GE0_MASK)
#define ETH_CFG_RMII_GE0_RESET					0x0 // 0
#define ETH_CFG_GE0_SGMII_MSB					6
#define ETH_CFG_GE0_SGMII_LSB					6
#define ETH_CFG_GE0_SGMII_MASK					0x00000040
#define ETH_CFG_GE0_SGMII_GET(x)				(((x) & ETH_CFG_GE0_SGMII_MASK) >> ETH_CFG_GE0_SGMII_LSB)
#define ETH_CFG_GE0_SGMII_SET(x)				(((x) << ETH_CFG_GE0_SGMII_LSB) & ETH_CFG_GE0_SGMII_MASK)
#define ETH_CFG_GE0_SGMII_RESET					0x0 // 0
#define ETH_CFG_GE0_ERR_EN_MSB					5
#define ETH_CFG_GE0_ERR_EN_LSB					5
#define ETH_CFG_GE0_ERR_EN_MASK					0x00000020
#define ETH_CFG_GE0_ERR_EN_GET(x)				(((x) & ETH_CFG_GE0_ERR_EN_MASK) >> ETH_CFG_GE0_ERR_EN_LSB)
#define ETH_CFG_GE0_ERR_EN_SET(x)				(((x) << ETH_CFG_GE0_ERR_EN_LSB) & ETH_CFG_GE0_ERR_EN_MASK)
#define ETH_CFG_GE0_ERR_EN_RESET				0x0 // 0
#define ETH_CFG_MII_GE0_SLAVE_MSB				4
#define ETH_CFG_MII_GE0_SLAVE_LSB				4
#define ETH_CFG_MII_GE0_SLAVE_MASK				0x00000010
#define ETH_CFG_MII_GE0_SLAVE_GET(x)				(((x) & ETH_CFG_MII_GE0_SLAVE_MASK) >> ETH_CFG_MII_GE0_SLAVE_LSB)
#define ETH_CFG_MII_GE0_SLAVE_SET(x)				(((x) << ETH_CFG_MII_GE0_SLAVE_LSB) & ETH_CFG_MII_GE0_SLAVE_MASK)
#define ETH_CFG_MII_GE0_SLAVE_RESET				0x0 // 0
#define ETH_CFG_MII_GE0_MASTER_MSB				3
#define ETH_CFG_MII_GE0_MASTER_LSB				3
#define ETH_CFG_MII_GE0_MASTER_MASK				0x00000008
#define ETH_CFG_MII_GE0_MASTER_GET(x)				(((x) & ETH_CFG_MII_GE0_MASTER_MASK) >> ETH_CFG_MII_GE0_MASTER_LSB)
#define ETH_CFG_MII_GE0_MASTER_SET(x)				(((x) << ETH_CFG_MII_GE0_MASTER_LSB) & ETH_CFG_MII_GE0_MASTER_MASK)
#define ETH_CFG_MII_GE0_MASTER_RESET				0x0 // 0
#define ETH_CFG_GMII_GE0_MSB					2
#define ETH_CFG_GMII_GE0_LSB					2
#define ETH_CFG_GMII_GE0_MASK					0x00000004
#define ETH_CFG_GMII_GE0_GET(x)					(((x) & ETH_CFG_GMII_GE0_MASK) >> ETH_CFG_GMII_GE0_LSB)
#define ETH_CFG_GMII_GE0_SET(x)					(((x) << ETH_CFG_GMII_GE0_LSB) & ETH_CFG_GMII_GE0_MASK)
#define ETH_CFG_GMII_GE0_RESET					0x0 // 0
#define ETH_CFG_MII_GE0_MSB					1
#define ETH_CFG_MII_GE0_LSB					1
#define ETH_CFG_MII_GE0_MASK					0x00000002
#define ETH_CFG_MII_GE0_GET(x)					(((x) & ETH_CFG_MII_GE0_MASK) >> ETH_CFG_MII_GE0_LSB)
#define ETH_CFG_MII_GE0_SET(x)					(((x) << ETH_CFG_MII_GE0_LSB) & ETH_CFG_MII_GE0_MASK)
#define ETH_CFG_MII_GE0_RESET					0x0 // 0
#define ETH_CFG_RGMII_GE0_MSB					0
#define ETH_CFG_RGMII_GE0_LSB					0
#define ETH_CFG_RGMII_GE0_MASK					0x00000001
#define ETH_CFG_RGMII_GE0_GET(x)				(((x) & ETH_CFG_RGMII_GE0_MASK) >> ETH_CFG_RGMII_GE0_LSB)
#define ETH_CFG_RGMII_GE0_SET(x)				(((x) << ETH_CFG_RGMII_GE0_LSB) & ETH_CFG_RGMII_GE0_MASK)
#define ETH_CFG_RGMII_GE0_RESET					0x0 // 0
#define ETH_CFG_ADDRESS						0x18070000

// 0x180b8024	MDIO_PHY_ADDR
#define MDIO_PHY_ADDR_VALUE_MSB					2
#define MDIO_PHY_ADDR_VALUE_LSB					0
#define MDIO_PHY_ADDR_VALUE_MASK				0x00000007
#define MDIO_PHY_ADDR_VALUE_GET(x)				(((x) & MDIO_PHY_ADDR_VALUE_MASK) >> MDIO_PHY_ADDR_VALUE_LSB)
#define MDIO_PHY_ADDR_VALUE_SET(x)				(((x) << MDIO_PHY_ADDR_VALUE_LSB) & MDIO_PHY_ADDR_VALUE_MASK)
#define MDIO_PHY_ADDR_VALUE_RESET				0x7 // 7
#define MDIO_PHY_ADDR_ADDRESS					0x180b8024

// 0x180c0000	PCIE_RC_REG_0
#define PCIE_RC_REG_0_DATA_MSB					31
#define PCIE_RC_REG_0_DATA_LSB					0
#define PCIE_RC_REG_0_DATA_MASK					0xffffffff
#define PCIE_RC_REG_0_DATA_GET(x)				(((x) & PCIE_RC_REG_0_DATA_MASK) >> PCIE_RC_REG_0_DATA_LSB)
#define PCIE_RC_REG_0_DATA_SET(x)				(((x) << PCIE_RC_REG_0_DATA_LSB) & PCIE_RC_REG_0_DATA_MASK)
#define PCIE_RC_REG_0_DATA_RESET				0x0 // 0
#define PCIE_RC_REG_0_ADDRESS					0x180c0000

// 0x180f0000	PCIE_APP
#define PCIE_APP_CFG_TYPE_MSB					21
#define PCIE_APP_CFG_TYPE_LSB					20
#define PCIE_APP_CFG_TYPE_MASK					0x00300000
#define PCIE_APP_CFG_TYPE_GET(x)				(((x) & PCIE_APP_CFG_TYPE_MASK) >> PCIE_APP_CFG_TYPE_LSB)
#define PCIE_APP_CFG_TYPE_SET(x)				(((x) << PCIE_APP_CFG_TYPE_LSB) & PCIE_APP_CFG_TYPE_MASK)
#define PCIE_APP_CFG_TYPE_RESET					0x0 // 0
#define PCIE_APP_PCIE_BAR_MSN_MSB				19
#define PCIE_APP_PCIE_BAR_MSN_LSB				16
#define PCIE_APP_PCIE_BAR_MSN_MASK				0x000f0000
#define PCIE_APP_PCIE_BAR_MSN_GET(x)				(((x) & PCIE_APP_PCIE_BAR_MSN_MASK) >> PCIE_APP_PCIE_BAR_MSN_LSB)
#define PCIE_APP_PCIE_BAR_MSN_SET(x)				(((x) << PCIE_APP_PCIE_BAR_MSN_LSB) & PCIE_APP_PCIE_BAR_MSN_MASK)
#define PCIE_APP_PCIE_BAR_MSN_RESET				0x1 // 1
#define PCIE_APP_CFG_BE_MSB					15
#define PCIE_APP_CFG_BE_LSB					12
#define PCIE_APP_CFG_BE_MASK					0x0000f000
#define PCIE_APP_CFG_BE_GET(x)					(((x) & PCIE_APP_CFG_BE_MASK) >> PCIE_APP_CFG_BE_LSB)
#define PCIE_APP_CFG_BE_SET(x)					(((x) << PCIE_APP_CFG_BE_LSB) & PCIE_APP_CFG_BE_MASK)
#define PCIE_APP_CFG_BE_RESET					0xf // 15
#define PCIE_APP_SLV_RESP_ERR_MAP_MSB				11
#define PCIE_APP_SLV_RESP_ERR_MAP_LSB				6
#define PCIE_APP_SLV_RESP_ERR_MAP_MASK				0x00000fc0
#define PCIE_APP_SLV_RESP_ERR_MAP_GET(x)			(((x) & PCIE_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_APP_SLV_RESP_ERR_MAP_LSB)
#define PCIE_APP_SLV_RESP_ERR_MAP_SET(x)			(((x) << PCIE_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_APP_SLV_RESP_ERR_MAP_MASK)
#define PCIE_APP_MSTR_RESP_ERR_MAP_MSB				5
#define PCIE_APP_MSTR_RESP_ERR_MAP_LSB				4
#define PCIE_APP_MSTR_RESP_ERR_MAP_MASK				0x00000030
#define PCIE_APP_MSTR_RESP_ERR_MAP_GET(x)			(((x) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_APP_MSTR_RESP_ERR_MAP_LSB)
#define PCIE_APP_MSTR_RESP_ERR_MAP_SET(x)			(((x) << PCIE_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_APP_MSTR_RESP_ERR_MAP_MASK)
#define PCIE_APP_MSTR_RESP_ERR_MAP_RESET			0x0 // 0
#define PCIE_APP_INIT_RST_MSB					3
#define PCIE_APP_INIT_RST_LSB					3
#define PCIE_APP_INIT_RST_MASK					0x00000008
#define PCIE_APP_INIT_RST_GET(x)				(((x) & PCIE_APP_INIT_RST_MASK) >> PCIE_APP_INIT_RST_LSB)
#define PCIE_APP_INIT_RST_SET(x)				(((x) << PCIE_APP_INIT_RST_LSB) & PCIE_APP_INIT_RST_MASK)
#define PCIE_APP_INIT_RST_RESET					0x0 // 0
#define PCIE_APP_PM_XMT_TURNOFF_MSB				2
#define PCIE_APP_PM_XMT_TURNOFF_LSB				2
#define PCIE_APP_PM_XMT_TURNOFF_MASK				0x00000004
#define PCIE_APP_PM_XMT_TURNOFF_GET(x)				(((x) & PCIE_APP_PM_XMT_TURNOFF_MASK) >> PCIE_APP_PM_XMT_TURNOFF_LSB)
#define PCIE_APP_PM_XMT_TURNOFF_SET(x)				(((x) << PCIE_APP_PM_XMT_TURNOFF_LSB) & PCIE_APP_PM_XMT_TURNOFF_MASK)
#define PCIE_APP_PM_XMT_TURNOFF_RESET				0x0 // 0
#define PCIE_APP_UNLOCK_MSG_MSB					1
#define PCIE_APP_UNLOCK_MSG_LSB					1
#define PCIE_APP_UNLOCK_MSG_MASK				0x00000002
#define PCIE_APP_UNLOCK_MSG_GET(x)				(((x) & PCIE_APP_UNLOCK_MSG_MASK) >> PCIE_APP_UNLOCK_MSG_LSB)
#define PCIE_APP_UNLOCK_MSG_SET(x)				(((x) << PCIE_APP_UNLOCK_MSG_LSB) & PCIE_APP_UNLOCK_MSG_MASK)
#define PCIE_APP_UNLOCK_MSG_RESET				0x0 // 0
#define PCIE_APP_LTSSM_ENABLE_MSB				0
#define PCIE_APP_LTSSM_ENABLE_LSB				0
#define PCIE_APP_LTSSM_ENABLE_MASK				0x00000001
#define PCIE_APP_LTSSM_ENABLE_GET(x)				(((x) & PCIE_APP_LTSSM_ENABLE_MASK) >> PCIE_APP_LTSSM_ENABLE_LSB)
#define PCIE_APP_LTSSM_ENABLE_SET(x)				(((x) << PCIE_APP_LTSSM_ENABLE_LSB) & PCIE_APP_LTSSM_ENABLE_MASK)
#define PCIE_APP_LTSSM_ENABLE_RESET				0x0 // 0
#define PCIE_APP_ADDRESS					0x180f0000


// 0x180f0008	PCIE_PWR_MGMT
#define PCIE_PWR_MGMT_PME_INT_MSB				8
#define PCIE_PWR_MGMT_PME_INT_LSB				8
#define PCIE_PWR_MGMT_PME_INT_MASK				0x00000100
#define PCIE_PWR_MGMT_PME_INT_GET(x)				(((x) & PCIE_PWR_MGMT_PME_INT_MASK) >> PCIE_PWR_MGMT_PME_INT_LSB)
#define PCIE_PWR_MGMT_PME_INT_SET(x)				(((x) << PCIE_PWR_MGMT_PME_INT_LSB) & PCIE_PWR_MGMT_PME_INT_MASK)
#define PCIE_PWR_MGMT_PME_INT_RESET				0x0 // 0
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MSB			7
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB			7
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK			0x00000080
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_GET(x)			(((x) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB)
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(x)			(((x) << PCIE_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_PWR_MGMT_ASSERT_CLKREQN_MASK)
#define PCIE_PWR_MGMT_ASSERT_CLKREQN_RESET			0x0 // 0
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MSB			6
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB			6
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK			0x00000040
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_GET(x)			(((x) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB)
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_SET(x)			(((x) << PCIE_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_PWR_MGMT_RADM_PM_TO_ACK_MASK)
#define PCIE_PWR_MGMT_RADM_PM_TO_ACK_RESET			0x0 // 0
#define PCIE_PWR_MGMT_RADM_PM_PME_MSB				5
#define PCIE_PWR_MGMT_RADM_PM_PME_LSB				5
#define PCIE_PWR_MGMT_RADM_PM_PME_MASK				0x00000020
#define PCIE_PWR_MGMT_RADM_PM_PME_GET(x)			(((x) & PCIE_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_PWR_MGMT_RADM_PM_PME_LSB)
#define PCIE_PWR_MGMT_RADM_PM_PME_SET(x)			(((x) << PCIE_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_PWR_MGMT_RADM_PM_PME_MASK)
#define PCIE_PWR_MGMT_RADM_PM_PME_RESET				0x0 // 0
#define PCIE_PWR_MGMT_AUX_PM_EN_MSB				4
#define PCIE_PWR_MGMT_AUX_PM_EN_LSB				4
#define PCIE_PWR_MGMT_AUX_PM_EN_MASK				0x00000010
#define PCIE_PWR_MGMT_AUX_PM_EN_GET(x)				(((x) & PCIE_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_PWR_MGMT_AUX_PM_EN_LSB)
#define PCIE_PWR_MGMT_AUX_PM_EN_SET(x)				(((x) << PCIE_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_PWR_MGMT_AUX_PM_EN_MASK)
#define PCIE_PWR_MGMT_AUX_PM_EN_RESET				0x0 // 0
#define PCIE_PWR_MGMT_READY_ENTR_L23_MSB			3
#define PCIE_PWR_MGMT_READY_ENTR_L23_LSB			3
#define PCIE_PWR_MGMT_READY_ENTR_L23_MASK			0x00000008
#define PCIE_PWR_MGMT_READY_ENTR_L23_GET(x)			(((x) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_PWR_MGMT_READY_ENTR_L23_LSB)
#define PCIE_PWR_MGMT_READY_ENTR_L23_SET(x)			(((x) << PCIE_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_PWR_MGMT_READY_ENTR_L23_MASK)
#define PCIE_PWR_MGMT_READY_ENTR_L23_RESET			0x0 // 0
#define PCIE_PWR_MGMT_REQ_EXIT_L1_MSB				2
#define PCIE_PWR_MGMT_REQ_EXIT_L1_LSB				2
#define PCIE_PWR_MGMT_REQ_EXIT_L1_MASK				0x00000004
#define PCIE_PWR_MGMT_REQ_EXIT_L1_GET(x)			(((x) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_PWR_MGMT_REQ_EXIT_L1_LSB)
#define PCIE_PWR_MGMT_REQ_EXIT_L1_SET(x)			(((x) << PCIE_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_PWR_MGMT_REQ_EXIT_L1_MASK)
#define PCIE_PWR_MGMT_REQ_EXIT_L1_RESET				0x0 // 0
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MSB				1
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB				1
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK				0x00000002
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_GET(x)			(((x) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB)
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_SET(x)			(((x) << PCIE_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_PWR_MGMT_REQ_ENTRY_L1_MASK)
#define PCIE_PWR_MGMT_REQ_ENTRY_L1_RESET			0x0 // 0
#define PCIE_PWR_MGMT_AUX_PWR_DET_MSB				0
#define PCIE_PWR_MGMT_AUX_PWR_DET_LSB				0
#define PCIE_PWR_MGMT_AUX_PWR_DET_MASK				0x00000001
#define PCIE_PWR_MGMT_AUX_PWR_DET_GET(x)			(((x) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_PWR_MGMT_AUX_PWR_DET_LSB)
#define PCIE_PWR_MGMT_AUX_PWR_DET_SET(x)			(((x) << PCIE_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_PWR_MGMT_AUX_PWR_DET_MASK)
#define PCIE_PWR_MGMT_AUX_PWR_DET_RESET				0x0 // 0
#define PCIE_PWR_MGMT_ADDRESS					0x180f0008


// 0x180f0018	PCIE_RESET
#define PCIE_RESET_EP_RESET_L_MSB				2
#define PCIE_RESET_EP_RESET_L_LSB				2
#define PCIE_RESET_EP_RESET_L_MASK				0x00000004
#define PCIE_RESET_EP_RESET_L_GET(x)				(((x) & PCIE_RESET_EP_RESET_L_MASK) >> PCIE_RESET_EP_RESET_L_LSB)
#define PCIE_RESET_EP_RESET_L_SET(x)				(((x) << PCIE_RESET_EP_RESET_L_LSB) & PCIE_RESET_EP_RESET_L_MASK)
#define PCIE_RESET_EP_RESET_L_RESET				0x0 // 0
#define PCIE_RESET_LINK_REQ_RESET_MSB				1
#define PCIE_RESET_LINK_REQ_RESET_LSB				1
#define PCIE_RESET_LINK_REQ_RESET_MASK				0x00000002
#define PCIE_RESET_LINK_REQ_RESET_GET(x)			(((x) & PCIE_RESET_LINK_REQ_RESET_MASK) >> PCIE_RESET_LINK_REQ_RESET_LSB)
#define PCIE_RESET_LINK_REQ_RESET_SET(x)			(((x) << PCIE_RESET_LINK_REQ_RESET_LSB) & PCIE_RESET_LINK_REQ_RESET_MASK)
#define PCIE_RESET_LINK_REQ_RESET_RESET				0x0 // 0
#define PCIE_RESET_LINK_UP_MSB					0
#define PCIE_RESET_LINK_UP_LSB					0
#define PCIE_RESET_LINK_UP_MASK					0x00000001
#define PCIE_RESET_LINK_UP_GET(x)				(((x) & PCIE_RESET_LINK_UP_MASK) >> PCIE_RESET_LINK_UP_LSB)
#define PCIE_RESET_LINK_UP_SET(x)				(((x) << PCIE_RESET_LINK_UP_LSB) & PCIE_RESET_LINK_UP_MASK)
#define PCIE_RESET_LINK_UP_RESET				0x0 // 0
#define PCIE_RESET_ADDRESS					0x180f0018


// 0x18107040	RTC_SYNC_RESET
#define RTC_SYNC_RESET_RESET_L_MSB				0
#define RTC_SYNC_RESET_RESET_L_LSB				0
#define RTC_SYNC_RESET_RESET_L_MASK				0x00000001
#define RTC_SYNC_RESET_RESET_L_GET(x)				(((x) & RTC_SYNC_RESET_RESET_L_MASK) >> RTC_SYNC_RESET_RESET_L_LSB)
#define RTC_SYNC_RESET_RESET_L_SET(x)				(((x) << RTC_SYNC_RESET_RESET_L_LSB) & RTC_SYNC_RESET_RESET_L_MASK)
#define RTC_SYNC_RESET_RESET_L_RESET				0x0 // 0
#define RTC_SYNC_RESET_ADDRESS					0x18107040

// 0x18107044	RTC_SYNC_STATUS
#define RTC_SYNC_STATUS_PLL_CHANGING_MSB			5
#define RTC_SYNC_STATUS_PLL_CHANGING_LSB			5
#define RTC_SYNC_STATUS_PLL_CHANGING_MASK			0x00000020
#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x)			(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> RTC_SYNC_STATUS_PLL_CHANGING_LSB)
#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x)			(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & RTC_SYNC_STATUS_PLL_CHANGING_MASK)
#define RTC_SYNC_STATUS_PLL_CHANGING_RESET			0x0 // 0
#define RTC_SYNC_STATUS_WRESET_MSB				4
#define RTC_SYNC_STATUS_WRESET_LSB				4
#define RTC_SYNC_STATUS_WRESET_MASK				0x00000010
#define RTC_SYNC_STATUS_WRESET_GET(x)				(((x) & RTC_SYNC_STATUS_WRESET_MASK) >> RTC_SYNC_STATUS_WRESET_LSB)
#define RTC_SYNC_STATUS_WRESET_SET(x)				(((x) << RTC_SYNC_STATUS_WRESET_LSB) & RTC_SYNC_STATUS_WRESET_MASK)
#define RTC_SYNC_STATUS_WRESET_RESET				0x0 // 0
#define RTC_SYNC_STATUS_WAKEUP_STATE_MSB			3
#define RTC_SYNC_STATUS_WAKEUP_STATE_LSB			3
#define RTC_SYNC_STATUS_WAKEUP_STATE_MASK			0x00000008
#define RTC_SYNC_STATUS_WAKEUP_STATE_GET(x)			(((x) & RTC_SYNC_STATUS_WAKEUP_STATE_MASK) >> RTC_SYNC_STATUS_WAKEUP_STATE_LSB)
#define RTC_SYNC_STATUS_WAKEUP_STATE_SET(x)			(((x) << RTC_SYNC_STATUS_WAKEUP_STATE_LSB) & RTC_SYNC_STATUS_WAKEUP_STATE_MASK)
#define RTC_SYNC_STATUS_WAKEUP_STATE_RESET			0x0 // 0
#define RTC_SYNC_STATUS_SLEEP_STATE_MSB				2
#define RTC_SYNC_STATUS_SLEEP_STATE_LSB				2
#define RTC_SYNC_STATUS_SLEEP_STATE_MASK			0x00000004
#define RTC_SYNC_STATUS_SLEEP_STATE_GET(x)			(((x) & RTC_SYNC_STATUS_SLEEP_STATE_MASK) >> RTC_SYNC_STATUS_SLEEP_STATE_LSB)
#define RTC_SYNC_STATUS_SLEEP_STATE_SET(x)			(((x) << RTC_SYNC_STATUS_SLEEP_STATE_LSB) & RTC_SYNC_STATUS_SLEEP_STATE_MASK)
#define RTC_SYNC_STATUS_SLEEP_STATE_RESET			0x0 // 0
#define RTC_SYNC_STATUS_ON_STATE_MSB				1
#define RTC_SYNC_STATUS_ON_STATE_LSB				1
#define RTC_SYNC_STATUS_ON_STATE_MASK				0x00000002
#define RTC_SYNC_STATUS_ON_STATE_GET(x)				(((x) & RTC_SYNC_STATUS_ON_STATE_MASK) >> RTC_SYNC_STATUS_ON_STATE_LSB)
#define RTC_SYNC_STATUS_ON_STATE_SET(x)				(((x) << RTC_SYNC_STATUS_ON_STATE_LSB) & RTC_SYNC_STATUS_ON_STATE_MASK)
#define RTC_SYNC_STATUS_ON_STATE_RESET				0x0 // 0
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_MSB			0
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_LSB			0
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_MASK			0x00000001
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_GET(x)			(((x) & RTC_SYNC_STATUS_SHUTDOWN_STATE_MASK) >> RTC_SYNC_STATUS_SHUTDOWN_STATE_LSB)
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_SET(x)			(((x) << RTC_SYNC_STATUS_SHUTDOWN_STATE_LSB) & RTC_SYNC_STATUS_SHUTDOWN_STATE_MASK)
#define RTC_SYNC_STATUS_SHUTDOWN_STATE_RESET			0x0 // 0
#define RTC_SYNC_STATUS_ADDRESS					0x18107044

// 0x18116cc0	PMU1
#define PMU1_SWREG_MSB						31
#define PMU1_SWREG_LSB						0
#define PMU1_SWREG_MASK						0xffffffff
#define PMU1_SWREG_GET(x)					(((x) & PMU1_SWREG_MASK) >> PMU1_SWREG_LSB)
#define PMU1_SWREG_SET(x)					(((x) << PMU1_SWREG_LSB) & PMU1_SWREG_MASK)
#define PMU1_ADDRESS						0x18116cc0

// 0x18116cc4	PMU2
#define PMU2_SWREGMSB_MSB					31
#define PMU2_SWREGMSB_LSB					22
#define PMU2_SWREGMSB_MASK					0xffc00000
#define PMU2_SWREGMSB_GET(x)					(((x) & PMU2_SWREGMSB_MASK) >> PMU2_SWREGMSB_LSB)
#define PMU2_SWREGMSB_SET(x)					(((x) << PMU2_SWREGMSB_LSB) & PMU2_SWREGMSB_MASK)
#define PMU2_SWREGMSB_RESET					0x0 // 0
#define PMU2_PGM_MSB						21
#define PMU2_PGM_LSB						21
#define PMU2_PGM_MASK						0x00200000
#define PMU2_PGM_GET(x)						(((x) & PMU2_PGM_MASK) >> PMU2_PGM_LSB)
#define PMU2_PGM_SET(x)						(((x) << PMU2_PGM_LSB) & PMU2_PGM_MASK)
#define PMU2_PGM_RESET						0x0 // 0
#define PMU2_LDO_TUNE_MSB					20
#define PMU2_LDO_TUNE_LSB					19
#define PMU2_LDO_TUNE_MASK					0x00180000
#define PMU2_LDO_TUNE_GET(x)					(((x) & PMU2_LDO_TUNE_MASK) >> PMU2_LDO_TUNE_LSB)
#define PMU2_LDO_TUNE_SET(x)					(((x) << PMU2_LDO_TUNE_LSB) & PMU2_LDO_TUNE_MASK)
#define PMU2_LDO_TUNE_RESET					0x0 // 0
#define PMU2_PWDLDO_DDR_MSB					18
#define PMU2_PWDLDO_DDR_LSB					18
#define PMU2_PWDLDO_DDR_MASK					0x00040000
#define PMU2_PWDLDO_DDR_GET(x)					(((x) & PMU2_PWDLDO_DDR_MASK) >> PMU2_PWDLDO_DDR_LSB)
#define PMU2_PWDLDO_DDR_SET(x)					(((x) << PMU2_PWDLDO_DDR_LSB) & PMU2_PWDLDO_DDR_MASK)
#define PMU2_PWDLDO_DDR_RESET					0x0 // 0
#define PMU2_LPOPWD_MSB						17
#define PMU2_LPOPWD_LSB						17
#define PMU2_LPOPWD_MASK					0x00020000
#define PMU2_LPOPWD_GET(x)					(((x) & PMU2_LPOPWD_MASK) >> PMU2_LPOPWD_LSB)
#define PMU2_LPOPWD_SET(x)					(((x) << PMU2_LPOPWD_LSB) & PMU2_LPOPWD_MASK)
#define PMU2_LPOPWD_RESET					0x0 // 0
#define PMU2_SPARE_MSB						16
#define PMU2_SPARE_LSB						0
#define PMU2_SPARE_MASK						0x0001ffff
#define PMU2_SPARE_GET(x)					(((x) & PMU2_SPARE_MASK) >> PMU2_SPARE_LSB)
#define PMU2_SPARE_SET(x)					(((x) << PMU2_SPARE_LSB) & PMU2_SPARE_MASK)
#define PMU2_SPARE_RESET					0x0 // 0
#define PMU2_ADDRESS						0x18116cc4

// 0x18116d88	USB0_PHY_CTRL2
#define USB0_PHY_CTRL2_PWD_EXTBIAS_MSB				31
#define USB0_PHY_CTRL2_PWD_EXTBIAS_LSB				31
#define USB0_PHY_CTRL2_PWD_EXTBIAS_MASK				0x80000000
#define USB0_PHY_CTRL2_PWD_EXTBIAS_GET(x)			(((x) & USB0_PHY_CTRL2_PWD_EXTBIAS_MASK) >> USB0_PHY_CTRL2_PWD_EXTBIAS_LSB)
#define USB0_PHY_CTRL2_PWD_EXTBIAS_SET(x)			(((x) << USB0_PHY_CTRL2_PWD_EXTBIAS_LSB) & USB0_PHY_CTRL2_PWD_EXTBIAS_MASK)
#define USB0_PHY_CTRL2_PWD_EXTBIAS_RESET			0x0 // 0
#define USB0_PHY_CTRL2_TX_RSVD_MSB				30
#define USB0_PHY_CTRL2_TX_RSVD_LSB				27
#define USB0_PHY_CTRL2_TX_RSVD_MASK				0x78000000
#define USB0_PHY_CTRL2_TX_RSVD_GET(x)				(((x) & USB0_PHY_CTRL2_TX_RSVD_MASK) >> USB0_PHY_CTRL2_TX_RSVD_LSB)
#define USB0_PHY_CTRL2_TX_RSVD_SET(x)				(((x) << USB0_PHY_CTRL2_TX_RSVD_LSB) & USB0_PHY_CTRL2_TX_RSVD_MASK)
#define USB0_PHY_CTRL2_TX_RSVD_RESET				0x0 // 0
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_MSB			26
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_LSB			26
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_MASK			0x04000000
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_GET(x)			(((x) & USB0_PHY_CTRL2_TX_LCKDET_OVR_MASK) >> USB0_PHY_CTRL2_TX_LCKDET_OVR_LSB)
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_SET(x)			(((x) << USB0_PHY_CTRL2_TX_LCKDET_OVR_LSB) & USB0_PHY_CTRL2_TX_LCKDET_OVR_MASK)
#define USB0_PHY_CTRL2_TX_LCKDET_OVR_RESET			0x0 // 0
#define USB0_PHY_CTRL2_TX_MAN_CAL_MSB				25
#define USB0_PHY_CTRL2_TX_MAN_CAL_LSB				22
#define USB0_PHY_CTRL2_TX_MAN_CAL_MASK				0x03c00000
#define USB0_PHY_CTRL2_TX_MAN_CAL_GET(x)			(((x) & USB0_PHY_CTRL2_TX_MAN_CAL_MASK) >> USB0_PHY_CTRL2_TX_MAN_CAL_LSB)
#define USB0_PHY_CTRL2_TX_MAN_CAL_SET(x)			(((x) << USB0_PHY_CTRL2_TX_MAN_CAL_LSB) & USB0_PHY_CTRL2_TX_MAN_CAL_MASK)
#define USB0_PHY_CTRL2_TX_MAN_CAL_RESET				0x3 // 3
#define USB0_PHY_CTRL2_TX_CAL_SEL_MSB				21
#define USB0_PHY_CTRL2_TX_CAL_SEL_LSB				21
#define USB0_PHY_CTRL2_TX_CAL_SEL_MASK				0x00200000
#define USB0_PHY_CTRL2_TX_CAL_SEL_GET(x)			(((x) & USB0_PHY_CTRL2_TX_CAL_SEL_MASK) >> USB0_PHY_CTRL2_TX_CAL_SEL_LSB)
#define USB0_PHY_CTRL2_TX_CAL_SEL_SET(x)			(((x) << USB0_PHY_CTRL2_TX_CAL_SEL_LSB) & USB0_PHY_CTRL2_TX_CAL_SEL_MASK)
#define USB0_PHY_CTRL2_TX_CAL_SEL_RESET				0x1 // 1
#define USB0_PHY_CTRL2_TX_CAL_EN_MSB				20
#define USB0_PHY_CTRL2_TX_CAL_EN_LSB				20
#define USB0_PHY_CTRL2_TX_CAL_EN_MASK				0x00100000
#define USB0_PHY_CTRL2_TX_CAL_EN_GET(x)				(((x) & USB0_PHY_CTRL2_TX_CAL_EN_MASK) >> USB0_PHY_CTRL2_TX_CAL_EN_LSB)
#define USB0_PHY_CTRL2_TX_CAL_EN_SET(x)				(((x) << USB0_PHY_CTRL2_TX_CAL_EN_LSB) & USB0_PHY_CTRL2_TX_CAL_EN_MASK)
#define USB0_PHY_CTRL2_TX_CAL_EN_RESET				0x1 // 1
#define USB0_PHY_CTRL2_PWD_ISP_MSB				13
#define USB0_PHY_CTRL2_PWD_ISP_LSB				8
#define USB0_PHY_CTRL2_PWD_ISP_MASK				0x00003f00
#define USB0_PHY_CTRL2_PWD_ISP_GET(x)				(((x) & USB0_PHY_CTRL2_PWD_ISP_MASK) >> USB0_PHY_CTRL2_PWD_ISP_LSB)
#define USB0_PHY_CTRL2_PWD_ISP_SET(x)				(((x) << USB0_PHY_CTRL2_PWD_ISP_LSB) & USB0_PHY_CTRL2_PWD_ISP_MASK)
#define USB0_PHY_CTRL2_PWD_IPLL_MSB				7
#define USB0_PHY_CTRL2_PWD_IPLL_LSB				2
#define USB0_PHY_CTRL2_PWD_IPLL_MASK				0x000000fc
#define USB0_PHY_CTRL2_PWD_IPLL_GET(x)				(((x) & USB0_PHY_CTRL2_PWD_IPLL_MASK) >> USB0_PHY_CTRL2_PWD_IPLL_LSB)
#define USB0_PHY_CTRL2_PWD_IPLL_SET(x)				(((x) << USB0_PHY_CTRL2_PWD_IPLL_LSB) & USB0_PHY_CTRL2_PWD_IPLL_MASK)
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_MSB			1
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_LSB			1
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_MASK			0x00000002
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_GET(x)			(((x) & USB0_PHY_CTRL2_HSRXPHASE_PS_EN_MASK) >> USB0_PHY_CTRL2_HSRXPHASE_PS_EN_LSB)
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_SET(x)			(((x) << USB0_PHY_CTRL2_HSRXPHASE_PS_EN_LSB) & USB0_PHY_CTRL2_HSRXPHASE_PS_EN_MASK)
#define USB0_PHY_CTRL2_HSRXPHASE_PS_EN_RESET			0x0 // 0
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_MSB			0
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_LSB			0
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_MASK			0x00000001
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_GET(x)			(((x) & USB0_PHY_CTRL2_HSTXBIAS_PS_EN_MASK) >> USB0_PHY_CTRL2_HSTXBIAS_PS_EN_LSB)
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_SET(x)			(((x) << USB0_PHY_CTRL2_HSTXBIAS_PS_EN_LSB) & USB0_PHY_CTRL2_HSTXBIAS_PS_EN_MASK)
#define USB0_PHY_CTRL2_HSTXBIAS_PS_EN_RESET			0x0 // 0
#define USB0_PHY_CTRL2_ADDRESS					0x18116d88

// 0x18116dc0	PCIE_PHY_REG_1
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MSB			31
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB			31
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK			0x80000000
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB)
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_PHY_REG_1_SERDES_DIS_RXIMP_MASK)
#define PCIE_PHY_REG_1_SERDES_DIS_RXIMP_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MSB			30
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB			29
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK			0x60000000
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB)
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_PHY_REG_1_SERDES_TXDR_CTRL_MASK)
#define PCIE_PHY_REG_1_SERDES_TXDR_CTRL_RESET			0x0 // 0
#define PCIE_PHY_REG_1_PERSTDELAY_MSB				28
#define PCIE_PHY_REG_1_PERSTDELAY_LSB				27
#define PCIE_PHY_REG_1_PERSTDELAY_MASK				0x18000000
#define PCIE_PHY_REG_1_PERSTDELAY_GET(x)			(((x) & PCIE_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_PHY_REG_1_PERSTDELAY_LSB)
#define PCIE_PHY_REG_1_PERSTDELAY_SET(x)			(((x) << PCIE_PHY_REG_1_PERSTDELAY_LSB) & PCIE_PHY_REG_1_PERSTDELAY_MASK)
#define PCIE_PHY_REG_1_PERSTDELAY_RESET				0x2 // 2
#define PCIE_PHY_REG_1_CLKOBSSEL_MSB				26
#define PCIE_PHY_REG_1_CLKOBSSEL_LSB				25
#define PCIE_PHY_REG_1_CLKOBSSEL_MASK				0x06000000
#define PCIE_PHY_REG_1_CLKOBSSEL_GET(x)				(((x) & PCIE_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_PHY_REG_1_CLKOBSSEL_LSB)
#define PCIE_PHY_REG_1_CLKOBSSEL_SET(x)				(((x) << PCIE_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_PHY_REG_1_CLKOBSSEL_MASK)
#define PCIE_PHY_REG_1_CLKOBSSEL_RESET				0x0 // 0
#define PCIE_PHY_REG_1_DATAOBSEN_MSB				24
#define PCIE_PHY_REG_1_DATAOBSEN_LSB				24
#define PCIE_PHY_REG_1_DATAOBSEN_MASK				0x01000000
#define PCIE_PHY_REG_1_DATAOBSEN_GET(x)				(((x) & PCIE_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_PHY_REG_1_DATAOBSEN_LSB)
#define PCIE_PHY_REG_1_DATAOBSEN_SET(x)				(((x) << PCIE_PHY_REG_1_DATAOBSEN_LSB) & PCIE_PHY_REG_1_DATAOBSEN_MASK)
#define PCIE_PHY_REG_1_DATAOBSEN_RESET				0x0 // 0
#define PCIE_PHY_REG_1_FUNCTESTEN_MSB				23
#define PCIE_PHY_REG_1_FUNCTESTEN_LSB				23
#define PCIE_PHY_REG_1_FUNCTESTEN_MASK				0x00800000
#define PCIE_PHY_REG_1_FUNCTESTEN_GET(x)			(((x) & PCIE_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_PHY_REG_1_FUNCTESTEN_LSB)
#define PCIE_PHY_REG_1_FUNCTESTEN_SET(x)			(((x) << PCIE_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_PHY_REG_1_FUNCTESTEN_MASK)
#define PCIE_PHY_REG_1_FUNCTESTEN_RESET				0x0 // 0
#define PCIE_PHY_REG_1_SERDES_DISABLE_MSB			22
#define PCIE_PHY_REG_1_SERDES_DISABLE_LSB			22
#define PCIE_PHY_REG_1_SERDES_DISABLE_MASK			0x00400000
#define PCIE_PHY_REG_1_SERDES_DISABLE_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_PHY_REG_1_SERDES_DISABLE_LSB)
#define PCIE_PHY_REG_1_SERDES_DISABLE_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_PHY_REG_1_SERDES_DISABLE_MASK)
#define PCIE_PHY_REG_1_SERDES_DISABLE_RESET			0x0 // 0
#define PCIE_PHY_REG_1_RXCLKINV_MSB				21
#define PCIE_PHY_REG_1_RXCLKINV_LSB				21
#define PCIE_PHY_REG_1_RXCLKINV_MASK				0x00200000
#define PCIE_PHY_REG_1_RXCLKINV_GET(x)				(((x) & PCIE_PHY_REG_1_RXCLKINV_MASK) >> PCIE_PHY_REG_1_RXCLKINV_LSB)
#define PCIE_PHY_REG_1_RXCLKINV_SET(x)				(((x) << PCIE_PHY_REG_1_RXCLKINV_LSB) & PCIE_PHY_REG_1_RXCLKINV_MASK)
#define PCIE_PHY_REG_1_RXCLKINV_RESET				0x1 // 1
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MSB			20
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB			20
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK			0x00100000
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_GET(x)			(((x) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB)
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_SET(x)			(((x) << PCIE_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTRXCLKINV_MASK)
#define PCIE_PHY_REG_1_FUNCTESTRXCLKINV_RESET			0x0 // 0
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MSB			19
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB			19
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK			0x00080000
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_GET(x)			(((x) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB)
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_SET(x)			(((x) << PCIE_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_PHY_REG_1_FUNCTESTTXCLKINV_MASK)
#define PCIE_PHY_REG_1_FUNCTESTTXCLKINV_RESET			0x0 // 0
#define PCIE_PHY_REG_1_ENABLECLKREQ_MSB				18
#define PCIE_PHY_REG_1_ENABLECLKREQ_LSB				18
#define PCIE_PHY_REG_1_ENABLECLKREQ_MASK			0x00040000
#define PCIE_PHY_REG_1_ENABLECLKREQ_GET(x)			(((x) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_PHY_REG_1_ENABLECLKREQ_LSB)
#define PCIE_PHY_REG_1_ENABLECLKREQ_SET(x)			(((x) << PCIE_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_PHY_REG_1_ENABLECLKREQ_MASK)
#define PCIE_PHY_REG_1_ENABLECLKREQ_RESET			0x0 // 0
#define PCIE_PHY_REG_1_FORCELOOPBACK_MSB			17
#define PCIE_PHY_REG_1_FORCELOOPBACK_LSB			17
#define PCIE_PHY_REG_1_FORCELOOPBACK_MASK			0x00020000
#define PCIE_PHY_REG_1_FORCELOOPBACK_GET(x)			(((x) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_PHY_REG_1_FORCELOOPBACK_LSB)
#define PCIE_PHY_REG_1_FORCELOOPBACK_SET(x)			(((x) << PCIE_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_PHY_REG_1_FORCELOOPBACK_MASK)
#define PCIE_PHY_REG_1_FORCELOOPBACK_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SEL_CLK_MSB				16
#define PCIE_PHY_REG_1_SEL_CLK_LSB				15
#define PCIE_PHY_REG_1_SEL_CLK_MASK				0x00018000
#define PCIE_PHY_REG_1_SEL_CLK_GET(x)				(((x) & PCIE_PHY_REG_1_SEL_CLK_MASK) >> PCIE_PHY_REG_1_SEL_CLK_LSB)
#define PCIE_PHY_REG_1_SEL_CLK_SET(x)				(((x) << PCIE_PHY_REG_1_SEL_CLK_LSB) & PCIE_PHY_REG_1_SEL_CLK_MASK)
#define PCIE_PHY_REG_1_SEL_CLK_RESET				0x2 // 2
#define PCIE_PHY_REG_1_SERDES_RX_EQ_MSB				14
#define PCIE_PHY_REG_1_SERDES_RX_EQ_LSB				14
#define PCIE_PHY_REG_1_SERDES_RX_EQ_MASK			0x00004000
#define PCIE_PHY_REG_1_SERDES_RX_EQ_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_PHY_REG_1_SERDES_RX_EQ_LSB)
#define PCIE_PHY_REG_1_SERDES_RX_EQ_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_PHY_REG_1_SERDES_RX_EQ_MASK)
#define PCIE_PHY_REG_1_SERDES_RX_EQ_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MSB			13
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB			13
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK			0x00002000
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB)
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_PHY_REG_1_SERDES_EN_LCKDT_MASK)
#define PCIE_PHY_REG_1_SERDES_EN_LCKDT_RESET			0x1 // 1
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB		12
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB		12
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK		0x00001000
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x)		(((x) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x)		(((x) << PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)
#define PCIE_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET		0x0 // 0
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MSB			11
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB			11
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK			0x00000800
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB)
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_PHY_REG_1_SERDES_POWER_SAVE_MASK)
#define PCIE_PHY_REG_1_SERDES_POWER_SAVE_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SERDES_CDR_BW_MSB			10
#define PCIE_PHY_REG_1_SERDES_CDR_BW_LSB			9
#define PCIE_PHY_REG_1_SERDES_CDR_BW_MASK			0x00000600
#define PCIE_PHY_REG_1_SERDES_CDR_BW_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_PHY_REG_1_SERDES_CDR_BW_LSB)
#define PCIE_PHY_REG_1_SERDES_CDR_BW_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_PHY_REG_1_SERDES_CDR_BW_MASK)
#define PCIE_PHY_REG_1_SERDES_CDR_BW_RESET			0x3 // 3
#define PCIE_PHY_REG_1_SERDES_TH_LOS_MSB			8
#define PCIE_PHY_REG_1_SERDES_TH_LOS_LSB			7
#define PCIE_PHY_REG_1_SERDES_TH_LOS_MASK			0x00000180
#define PCIE_PHY_REG_1_SERDES_TH_LOS_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_PHY_REG_1_SERDES_TH_LOS_LSB)
#define PCIE_PHY_REG_1_SERDES_TH_LOS_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_PHY_REG_1_SERDES_TH_LOS_MASK)
#define PCIE_PHY_REG_1_SERDES_TH_LOS_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MSB			6
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB			6
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK			0x00000040
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB)
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_PHY_REG_1_SERDES_EN_DEEMP_MASK)
#define PCIE_PHY_REG_1_SERDES_EN_DEEMP_RESET			0x1 // 1
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MSB			5
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB			5
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK			0x00000020
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB)
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_PHY_REG_1_SERDES_HALFTXDR_MASK)
#define PCIE_PHY_REG_1_SERDES_HALFTXDR_RESET			0x0 // 0
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MSB			4
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB			4
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK			0x00000010
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_GET(x)			(((x) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB)
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_SET(x)			(((x) << PCIE_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_PHY_REG_1_SERDES_SEL_HSP_MASK)
#define PCIE_PHY_REG_1_SERDES_SEL_HSP_RESET			0x1 // 1
#define PCIE_PHY_REG_1_S_MSB					3
#define PCIE_PHY_REG_1_S_LSB					0
#define PCIE_PHY_REG_1_S_MASK					0x0000000f
#define PCIE_PHY_REG_1_S_GET(x)					(((x) & PCIE_PHY_REG_1_S_MASK) >> PCIE_PHY_REG_1_S_LSB)
#define PCIE_PHY_REG_1_S_SET(x)					(((x) << PCIE_PHY_REG_1_S_LSB) & PCIE_PHY_REG_1_S_MASK)
#define PCIE_PHY_REG_1_S_RESET					0xe // 14
#define PCIE_PHY_REG_1_ADDRESS					0x18116dc0


// 0x18116dc4	PCIE_PHY_REG_2
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MSB			31
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB			24
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK			0xff000000
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_GET(x)			(((x) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB)
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_SET(x)			(((x) << PCIE_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_PHY_REG_2_PRBS_ERROR_COUNT_MASK)
#define PCIE_PHY_REG_2_PRBS_ERROR_COUNT_RESET			0x0 // 0
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB			23
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB			23
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK			0x00800000
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x)		(((x) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB)
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x)		(((x) << PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK)
#define PCIE_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET			0x0 // 0
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MSB			22
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB			22
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK			0x00400000
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x)		(((x) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB)
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x)		(((x) << PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_MASK)
#define PCIE_PHY_REG_2_SDS_SDM_RXDETECTED_RESET			0x0 // 0
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MSB			21
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB			21
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK			0x00200000
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_GET(x)			(((x) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB)
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_SET(x)			(((x) << PCIE_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_PHY_REG_2_PRBS_SCRAMBLE_MASK)
#define PCIE_PHY_REG_2_PRBS_SCRAMBLE_RESET			0x0 // 0
#define PCIE_PHY_REG_2_PRBS_START_MSB				20
#define PCIE_PHY_REG_2_PRBS_START_LSB				20
#define PCIE_PHY_REG_2_PRBS_START_MASK				0x00100000
#define PCIE_PHY_REG_2_PRBS_START_GET(x)			(((x) & PCIE_PHY_REG_2_PRBS_START_MASK) >> PCIE_PHY_REG_2_PRBS_START_LSB)
#define PCIE_PHY_REG_2_PRBS_START_SET(x)			(((x) << PCIE_PHY_REG_2_PRBS_START_LSB) & PCIE_PHY_REG_2_PRBS_START_MASK)
#define PCIE_PHY_REG_2_PRBS_START_RESET				0x0 // 0
#define PCIE_PHY_REG_2_PRBS_TS_NUM_MSB				19
#define PCIE_PHY_REG_2_PRBS_TS_NUM_LSB				13
#define PCIE_PHY_REG_2_PRBS_TS_NUM_MASK				0x000fe000
#define PCIE_PHY_REG_2_PRBS_TS_NUM_GET(x)			(((x) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_PHY_REG_2_PRBS_TS_NUM_LSB)
#define PCIE_PHY_REG_2_PRBS_TS_NUM_SET(x)			(((x) << PCIE_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_PHY_REG_2_PRBS_TS_NUM_MASK)
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MSB			12
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB			12
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK			0x00001000
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_GET(x)			(((x) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB)
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_SET(x)			(((x) << PCIE_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_PHY_REG_2_TXDETRXOVRVALUE_MASK)
#define PCIE_PHY_REG_2_TXDETRXOVRVALUE_RESET			0x0 // 0
#define PCIE_PHY_REG_2_TXDETRXOVREN_MSB				11
#define PCIE_PHY_REG_2_TXDETRXOVREN_LSB				11
#define PCIE_PHY_REG_2_TXDETRXOVREN_MASK			0x00000800
#define PCIE_PHY_REG_2_TXDETRXOVREN_GET(x)			(((x) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_PHY_REG_2_TXDETRXOVREN_LSB)
#define PCIE_PHY_REG_2_TXDETRXOVREN_SET(x)			(((x) << PCIE_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_PHY_REG_2_TXDETRXOVREN_MASK)
#define PCIE_PHY_REG_2_TXDETRXOVREN_RESET			0x0 // 0
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MSB			10
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB			10
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK			0x00000400
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_GET(x)			(((x) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB)
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_SET(x)			(((x) << PCIE_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_PHY_REG_2_DATAOBSPRBSERR_MASK)
#define PCIE_PHY_REG_2_DATAOBSPRBSERR_RESET			0x0 // 0
#define PCIE_PHY_REG_2_CDRREADYTIMER_MSB			9
#define PCIE_PHY_REG_2_CDRREADYTIMER_LSB			6
#define PCIE_PHY_REG_2_CDRREADYTIMER_MASK			0x000003c0
#define PCIE_PHY_REG_2_CDRREADYTIMER_GET(x)			(((x) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_PHY_REG_2_CDRREADYTIMER_LSB)
#define PCIE_PHY_REG_2_CDRREADYTIMER_SET(x)			(((x) << PCIE_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_PHY_REG_2_CDRREADYTIMER_MASK)
#define PCIE_PHY_REG_2_CDRREADYTIMER_RESET			0x7 // 7
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MSB			5
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB			1
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK			0x0000003e
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_GET(x)		(((x) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB)
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_SET(x)		(((x) << PCIE_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_PHY_REG_2_TXDETRXTARGETDELAY_MASK)
#define PCIE_PHY_REG_2_TXDETRXTARGETDELAY_RESET			0xc // 12
#define PCIE_PHY_REG_2_FORCEDETECT_MSB				0
#define PCIE_PHY_REG_2_FORCEDETECT_LSB				0
#define PCIE_PHY_REG_2_FORCEDETECT_MASK				0x00000001
#define PCIE_PHY_REG_2_FORCEDETECT_GET(x)			(((x) & PCIE_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_PHY_REG_2_FORCEDETECT_LSB)
#define PCIE_PHY_REG_2_FORCEDETECT_SET(x)			(((x) << PCIE_PHY_REG_2_FORCEDETECT_LSB) & PCIE_PHY_REG_2_FORCEDETECT_MASK)
#define PCIE_PHY_REG_2_FORCEDETECT_RESET			0x0 // 0
#define PCIE_PHY_REG_2_ADDRESS					0x18116dc4


// 0x18116dc8	PCIE_PHY_REG_3
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MSB			31
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB			28
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK			0xf0000000
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_GET(x)			(((x) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB)
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_SET(x)			(((x) << PCIE_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_PHY_REG_3_PRBS_COMMA_STATUS_MASK)
#define PCIE_PHY_REG_3_PRBS_COMMA_STATUS_RESET			0x0 // 0
#define PCIE_PHY_REG_3_SPARE_MSB				27
#define PCIE_PHY_REG_3_SPARE_LSB				11
#define PCIE_PHY_REG_3_SPARE_MASK				0x0ffff800
#define PCIE_PHY_REG_3_SPARE_GET(x)				(((x) & PCIE_PHY_REG_3_SPARE_MASK) >> PCIE_PHY_REG_3_SPARE_LSB)
#define PCIE_PHY_REG_3_SPARE_SET(x)				(((x) << PCIE_PHY_REG_3_SPARE_LSB) & PCIE_PHY_REG_3_SPARE_MASK)
#define PCIE_PHY_REG_3_SEL_CLK100_MSB				10
#define PCIE_PHY_REG_3_SEL_CLK100_LSB				10
#define PCIE_PHY_REG_3_SEL_CLK100_MASK				0x00000400
#define PCIE_PHY_REG_3_SEL_CLK100_GET(x)			(((x) & PCIE_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_PHY_REG_3_SEL_CLK100_LSB)
#define PCIE_PHY_REG_3_SEL_CLK100_SET(x)			(((x) << PCIE_PHY_REG_3_SEL_CLK100_LSB) & PCIE_PHY_REG_3_SEL_CLK100_MASK)
#define PCIE_PHY_REG_3_SEL_CLK100_RESET				0x0 // 0
#define PCIE_PHY_REG_3_EN_BEACONGEN_MSB				9
#define PCIE_PHY_REG_3_EN_BEACONGEN_LSB				9
#define PCIE_PHY_REG_3_EN_BEACONGEN_MASK			0x00000200
#define PCIE_PHY_REG_3_EN_BEACONGEN_GET(x)			(((x) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_PHY_REG_3_EN_BEACONGEN_LSB)
#define PCIE_PHY_REG_3_EN_BEACONGEN_SET(x)			(((x) << PCIE_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_PHY_REG_3_EN_BEACONGEN_MASK)
#define PCIE_PHY_REG_3_EN_BEACONGEN_RESET			0x0 // 0
#define PCIE_PHY_REG_3_TXELECIDLE_MSB				8
#define PCIE_PHY_REG_3_TXELECIDLE_LSB				8
#define PCIE_PHY_REG_3_TXELECIDLE_MASK				0x00000100
#define PCIE_PHY_REG_3_TXELECIDLE_GET(x)			(((x) & PCIE_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_PHY_REG_3_TXELECIDLE_LSB)
#define PCIE_PHY_REG_3_TXELECIDLE_SET(x)			(((x) << PCIE_PHY_REG_3_TXELECIDLE_LSB) & PCIE_PHY_REG_3_TXELECIDLE_MASK)
#define PCIE_PHY_REG_3_TXELECIDLE_RESET				0x0 // 0
#define PCIE_PHY_REG_3_SEL_CLK_MSB				7
#define PCIE_PHY_REG_3_SEL_CLK_LSB				6
#define PCIE_PHY_REG_3_SEL_CLK_MASK				0x000000c0
#define PCIE_PHY_REG_3_SEL_CLK_GET(x)				(((x) & PCIE_PHY_REG_3_SEL_CLK_MASK) >> PCIE_PHY_REG_3_SEL_CLK_LSB)
#define PCIE_PHY_REG_3_SEL_CLK_SET(x)				(((x) << PCIE_PHY_REG_3_SEL_CLK_LSB) & PCIE_PHY_REG_3_SEL_CLK_MASK)
#define PCIE_PHY_REG_3_SEL_CLK_RESET				0x0 // 0
#define PCIE_PHY_REG_3_RX_DET_REQ_MSB				5
#define PCIE_PHY_REG_3_RX_DET_REQ_LSB				5
#define PCIE_PHY_REG_3_RX_DET_REQ_MASK				0x00000020
#define PCIE_PHY_REG_3_RX_DET_REQ_GET(x)			(((x) & PCIE_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_PHY_REG_3_RX_DET_REQ_LSB)
#define PCIE_PHY_REG_3_RX_DET_REQ_SET(x)			(((x) << PCIE_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_PHY_REG_3_RX_DET_REQ_MASK)
#define PCIE_PHY_REG_3_RX_DET_REQ_RESET				0x0 // 0
#define PCIE_PHY_REG_3_MODE_OCLK_IN_MSB				4
#define PCIE_PHY_REG_3_MODE_OCLK_IN_LSB				4
#define PCIE_PHY_REG_3_MODE_OCLK_IN_MASK			0x00000010
#define PCIE_PHY_REG_3_MODE_OCLK_IN_GET(x)			(((x) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_PHY_REG_3_MODE_OCLK_IN_LSB)
#define PCIE_PHY_REG_3_MODE_OCLK_IN_SET(x)			(((x) << PCIE_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_PHY_REG_3_MODE_OCLK_IN_MASK)
#define PCIE_PHY_REG_3_MODE_OCLK_IN_RESET			0x0 // 0
#define PCIE_PHY_REG_3_EN_PLL_MSB				3
#define PCIE_PHY_REG_3_EN_PLL_LSB				3
#define PCIE_PHY_REG_3_EN_PLL_MASK				0x00000008
#define PCIE_PHY_REG_3_EN_PLL_GET(x)				(((x) & PCIE_PHY_REG_3_EN_PLL_MASK) >> PCIE_PHY_REG_3_EN_PLL_LSB)
#define PCIE_PHY_REG_3_EN_PLL_SET(x)				(((x) << PCIE_PHY_REG_3_EN_PLL_LSB) & PCIE_PHY_REG_3_EN_PLL_MASK)
#define PCIE_PHY_REG_3_EN_PLL_RESET				0x1 // 1
#define PCIE_PHY_REG_3_EN_LCKDT_MSB				2
#define PCIE_PHY_REG_3_EN_LCKDT_LSB				2
#define PCIE_PHY_REG_3_EN_LCKDT_MASK				0x00000004
#define PCIE_PHY_REG_3_EN_LCKDT_GET(x)				(((x) & PCIE_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_PHY_REG_3_EN_LCKDT_LSB)
#define PCIE_PHY_REG_3_EN_LCKDT_SET(x)				(((x) << PCIE_PHY_REG_3_EN_LCKDT_LSB) & PCIE_PHY_REG_3_EN_LCKDT_MASK)
#define PCIE_PHY_REG_3_EN_LCKDT_RESET				0x1 // 1
#define PCIE_PHY_REG_3_EN_BUFS_RX_MSB				1
#define PCIE_PHY_REG_3_EN_BUFS_RX_LSB				1
#define PCIE_PHY_REG_3_EN_BUFS_RX_MASK				0x00000002
#define PCIE_PHY_REG_3_EN_BUFS_RX_GET(x)			(((x) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_PHY_REG_3_EN_BUFS_RX_LSB)
#define PCIE_PHY_REG_3_EN_BUFS_RX_SET(x)			(((x) << PCIE_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_PHY_REG_3_EN_BUFS_RX_MASK)
#define PCIE_PHY_REG_3_EN_BUFS_RX_RESET				0x0 // 0
#define PCIE_PHY_REG_3_EN_MSB					0
#define PCIE_PHY_REG_3_EN_LSB					0
#define PCIE_PHY_REG_3_EN_MASK					0x00000001
#define PCIE_PHY_REG_3_EN_GET(x)				(((x) & PCIE_PHY_REG_3_EN_MASK) >> PCIE_PHY_REG_3_EN_LSB)
#define PCIE_PHY_REG_3_EN_SET(x)				(((x) << PCIE_PHY_REG_3_EN_LSB) & PCIE_PHY_REG_3_EN_MASK)
#define PCIE_PHY_REG_3_EN_RESET					0x0 // 0
#define PCIE_PHY_REG_3_ADDRESS					0x18116dc8

// 0x18280000	PCIE_RC2_APP
#define PCIE_RC2_APP_CFG_TYPE_MSB				21
#define PCIE_RC2_APP_CFG_TYPE_LSB				20
#define PCIE_RC2_APP_CFG_TYPE_MASK				0x00300000
#define PCIE_RC2_APP_CFG_TYPE_GET(x)				(((x) & PCIE_RC2_APP_CFG_TYPE_MASK) >> PCIE_RC2_APP_CFG_TYPE_LSB)
#define PCIE_RC2_APP_CFG_TYPE_SET(x)				(((x) << PCIE_RC2_APP_CFG_TYPE_LSB) & PCIE_RC2_APP_CFG_TYPE_MASK)
#define PCIE_RC2_APP_CFG_TYPE_RESET				0x0 // 0
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_MSB			19
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_LSB			16
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_MASK			0x000f0000
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_GET(x)			(((x) & PCIE_RC2_APP_PCIE_RC2_BAR_MSN_MASK) >> PCIE_RC2_APP_PCIE_RC2_BAR_MSN_LSB)
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_SET(x)			(((x) << PCIE_RC2_APP_PCIE_RC2_BAR_MSN_LSB) & PCIE_RC2_APP_PCIE_RC2_BAR_MSN_MASK)
#define PCIE_RC2_APP_PCIE_RC2_BAR_MSN_RESET			0x1 // 1
#define PCIE_RC2_APP_CFG_BE_MSB					15
#define PCIE_RC2_APP_CFG_BE_LSB					12
#define PCIE_RC2_APP_CFG_BE_MASK				0x0000f000
#define PCIE_RC2_APP_CFG_BE_GET(x)				(((x) & PCIE_RC2_APP_CFG_BE_MASK) >> PCIE_RC2_APP_CFG_BE_LSB)
#define PCIE_RC2_APP_CFG_BE_SET(x)				(((x) << PCIE_RC2_APP_CFG_BE_LSB) & PCIE_RC2_APP_CFG_BE_MASK)
#define PCIE_RC2_APP_CFG_BE_RESET				0xf // 15
#define PCIE_RC2_APP_SLV_RESP_ERR_MAP_MSB			11
#define PCIE_RC2_APP_SLV_RESP_ERR_MAP_LSB			6
#define PCIE_RC2_APP_SLV_RESP_ERR_MAP_MASK			0x00000fc0
#define PCIE_RC2_APP_SLV_RESP_ERR_MAP_GET(x)			(((x) & PCIE_RC2_APP_SLV_RESP_ERR_MAP_MASK) >> PCIE_RC2_APP_SLV_RESP_ERR_MAP_LSB)
#define PCIE_RC2_APP_SLV_RESP_ERR_MAP_SET(x)			(((x) << PCIE_RC2_APP_SLV_RESP_ERR_MAP_LSB) & PCIE_RC2_APP_SLV_RESP_ERR_MAP_MASK)
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_MSB			5
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_LSB			4
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_MASK			0x00000030
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_GET(x)			(((x) & PCIE_RC2_APP_MSTR_RESP_ERR_MAP_MASK) >> PCIE_RC2_APP_MSTR_RESP_ERR_MAP_LSB)
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_SET(x)			(((x) << PCIE_RC2_APP_MSTR_RESP_ERR_MAP_LSB) & PCIE_RC2_APP_MSTR_RESP_ERR_MAP_MASK)
#define PCIE_RC2_APP_MSTR_RESP_ERR_MAP_RESET			0x0 // 0
#define PCIE_RC2_APP_INIT_RST_MSB				3
#define PCIE_RC2_APP_INIT_RST_LSB				3
#define PCIE_RC2_APP_INIT_RST_MASK				0x00000008
#define PCIE_RC2_APP_INIT_RST_GET(x)				(((x) & PCIE_RC2_APP_INIT_RST_MASK) >> PCIE_RC2_APP_INIT_RST_LSB)
#define PCIE_RC2_APP_INIT_RST_SET(x)				(((x) << PCIE_RC2_APP_INIT_RST_LSB) & PCIE_RC2_APP_INIT_RST_MASK)
#define PCIE_RC2_APP_INIT_RST_RESET				0x0 // 0
#define PCIE_RC2_APP_PM_XMT_TURNOFF_MSB				2
#define PCIE_RC2_APP_PM_XMT_TURNOFF_LSB				2
#define PCIE_RC2_APP_PM_XMT_TURNOFF_MASK			0x00000004
#define PCIE_RC2_APP_PM_XMT_TURNOFF_GET(x)			(((x) & PCIE_RC2_APP_PM_XMT_TURNOFF_MASK) >> PCIE_RC2_APP_PM_XMT_TURNOFF_LSB)
#define PCIE_RC2_APP_PM_XMT_TURNOFF_SET(x)			(((x) << PCIE_RC2_APP_PM_XMT_TURNOFF_LSB) & PCIE_RC2_APP_PM_XMT_TURNOFF_MASK)
#define PCIE_RC2_APP_PM_XMT_TURNOFF_RESET			0x0 // 0
#define PCIE_RC2_APP_UNLOCK_MSG_MSB				1
#define PCIE_RC2_APP_UNLOCK_MSG_LSB				1
#define PCIE_RC2_APP_UNLOCK_MSG_MASK				0x00000002
#define PCIE_RC2_APP_UNLOCK_MSG_GET(x)				(((x) & PCIE_RC2_APP_UNLOCK_MSG_MASK) >> PCIE_RC2_APP_UNLOCK_MSG_LSB)
#define PCIE_RC2_APP_UNLOCK_MSG_SET(x)				(((x) << PCIE_RC2_APP_UNLOCK_MSG_LSB) & PCIE_RC2_APP_UNLOCK_MSG_MASK)
#define PCIE_RC2_APP_UNLOCK_MSG_RESET				0x0 // 0
#define PCIE_RC2_APP_LTSSM_ENABLE_MSB				0
#define PCIE_RC2_APP_LTSSM_ENABLE_LSB				0
#define PCIE_RC2_APP_LTSSM_ENABLE_MASK				0x00000001
#define PCIE_RC2_APP_LTSSM_ENABLE_GET(x)			(((x) & PCIE_RC2_APP_LTSSM_ENABLE_MASK) >> PCIE_RC2_APP_LTSSM_ENABLE_LSB)
#define PCIE_RC2_APP_LTSSM_ENABLE_SET(x)			(((x) << PCIE_RC2_APP_LTSSM_ENABLE_LSB) & PCIE_RC2_APP_LTSSM_ENABLE_MASK)
#define PCIE_RC2_APP_LTSSM_ENABLE_RESET				0x0 // 0
#define PCIE_RC2_APP_ADDRESS					0x18280000

// 0x18280008	PCIE_RC2_PWR_MGMT
#define PCIE_RC2_PWR_MGMT_PME_INT_MSB				8
#define PCIE_RC2_PWR_MGMT_PME_INT_LSB				8
#define PCIE_RC2_PWR_MGMT_PME_INT_MASK				0x00000100
#define PCIE_RC2_PWR_MGMT_PME_INT_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_PME_INT_MASK) >> PCIE_RC2_PWR_MGMT_PME_INT_LSB)
#define PCIE_RC2_PWR_MGMT_PME_INT_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_PME_INT_LSB) & PCIE_RC2_PWR_MGMT_PME_INT_MASK)
#define PCIE_RC2_PWR_MGMT_PME_INT_RESET				0x0 // 0
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_MSB			7
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_LSB			7
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_MASK			0x00000080
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_MASK) >> PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_LSB)
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_LSB) & PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_MASK)
#define PCIE_RC2_PWR_MGMT_ASSERT_CLKREQN_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_MSB			6
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_LSB			6
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_MASK			0x00000040
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_MASK) >> PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_LSB)
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_LSB) & PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_MASK)
#define PCIE_RC2_PWR_MGMT_RADM_PM_TO_ACK_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_MSB			5
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_LSB			5
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_MASK			0x00000020
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_RADM_PM_PME_MASK) >> PCIE_RC2_PWR_MGMT_RADM_PM_PME_LSB)
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_RADM_PM_PME_LSB) & PCIE_RC2_PWR_MGMT_RADM_PM_PME_MASK)
#define PCIE_RC2_PWR_MGMT_RADM_PM_PME_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_MSB				4
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_LSB				4
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_MASK			0x00000010
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_AUX_PM_EN_MASK) >> PCIE_RC2_PWR_MGMT_AUX_PM_EN_LSB)
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_AUX_PM_EN_LSB) & PCIE_RC2_PWR_MGMT_AUX_PM_EN_MASK)
#define PCIE_RC2_PWR_MGMT_AUX_PM_EN_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_MSB			3
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_LSB			3
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_MASK			0x00000008
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_READY_ENTR_L23_MASK) >> PCIE_RC2_PWR_MGMT_READY_ENTR_L23_LSB)
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_READY_ENTR_L23_LSB) & PCIE_RC2_PWR_MGMT_READY_ENTR_L23_MASK)
#define PCIE_RC2_PWR_MGMT_READY_ENTR_L23_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_MSB			2
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_LSB			2
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_MASK			0x00000004
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_MASK) >> PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_LSB)
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_LSB) & PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_MASK)
#define PCIE_RC2_PWR_MGMT_REQ_EXIT_L1_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_MSB			1
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_LSB			1
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_MASK			0x00000002
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_MASK) >> PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_LSB)
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_LSB) & PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_MASK)
#define PCIE_RC2_PWR_MGMT_REQ_ENTRY_L1_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_MSB			0
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_LSB			0
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_MASK			0x00000001
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_GET(x)			(((x) & PCIE_RC2_PWR_MGMT_AUX_PWR_DET_MASK) >> PCIE_RC2_PWR_MGMT_AUX_PWR_DET_LSB)
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_SET(x)			(((x) << PCIE_RC2_PWR_MGMT_AUX_PWR_DET_LSB) & PCIE_RC2_PWR_MGMT_AUX_PWR_DET_MASK)
#define PCIE_RC2_PWR_MGMT_AUX_PWR_DET_RESET			0x0 // 0
#define PCIE_RC2_PWR_MGMT_ADDRESS				0x18280008

// 0x18280018	PCIE_RC2_RESET
#define PCIE_RC2_RESET_EP_RESET_L_MSB				2
#define PCIE_RC2_RESET_EP_RESET_L_LSB				2
#define PCIE_RC2_RESET_EP_RESET_L_MASK				0x00000004
#define PCIE_RC2_RESET_EP_RESET_L_GET(x)			(((x) & PCIE_RC2_RESET_EP_RESET_L_MASK) >> PCIE_RC2_RESET_EP_RESET_L_LSB)
#define PCIE_RC2_RESET_EP_RESET_L_SET(x)			(((x) << PCIE_RC2_RESET_EP_RESET_L_LSB) & PCIE_RC2_RESET_EP_RESET_L_MASK)
#define PCIE_RC2_RESET_EP_RESET_L_RESET				0x0 // 0
#define PCIE_RC2_RESET_LINK_REQ_RESET_MSB			1
#define PCIE_RC2_RESET_LINK_REQ_RESET_LSB			1
#define PCIE_RC2_RESET_LINK_REQ_RESET_MASK			0x00000002
#define PCIE_RC2_RESET_LINK_REQ_RESET_GET(x)			(((x) & PCIE_RC2_RESET_LINK_REQ_RESET_MASK) >> PCIE_RC2_RESET_LINK_REQ_RESET_LSB)
#define PCIE_RC2_RESET_LINK_REQ_RESET_SET(x)			(((x) << PCIE_RC2_RESET_LINK_REQ_RESET_LSB) & PCIE_RC2_RESET_LINK_REQ_RESET_MASK)
#define PCIE_RC2_RESET_LINK_REQ_RESET_RESET			0x0 // 0
#define PCIE_RC2_RESET_LINK_UP_MSB				0
#define PCIE_RC2_RESET_LINK_UP_LSB				0
#define PCIE_RC2_RESET_LINK_UP_MASK				0x00000001
#define PCIE_RC2_RESET_LINK_UP_GET(x)				(((x) & PCIE_RC2_RESET_LINK_UP_MASK) >> PCIE_RC2_RESET_LINK_UP_LSB)
#define PCIE_RC2_RESET_LINK_UP_SET(x)				(((x) << PCIE_RC2_RESET_LINK_UP_LSB) & PCIE_RC2_RESET_LINK_UP_MASK)
#define PCIE_RC2_RESET_LINK_UP_RESET				0x0 // 0
#define PCIE_RC2_RESET_ADDRESS					0x18280018

// 0x18116e00	PCIE_RC2_PHY_REG_1
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_MSB			31
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_LSB			31
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_MASK		0x80000000
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_LSB) & PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_DIS_RXIMP_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_MSB			30
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_LSB			29
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_MASK		0x60000000
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_LSB) & PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_TXDR_CTRL_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_MSB			28
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_LSB			27
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_MASK			0x18000000
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_PERSTDELAY_MASK) >> PCIE_RC2_PHY_REG_1_PERSTDELAY_LSB)
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_PERSTDELAY_LSB) & PCIE_RC2_PHY_REG_1_PERSTDELAY_MASK)
#define PCIE_RC2_PHY_REG_1_PERSTDELAY_RESET			0x2 // 2
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_MSB			26
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_LSB			25
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_MASK			0x06000000
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_CLKOBSSEL_MASK) >> PCIE_RC2_PHY_REG_1_CLKOBSSEL_LSB)
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_CLKOBSSEL_LSB) & PCIE_RC2_PHY_REG_1_CLKOBSSEL_MASK)
#define PCIE_RC2_PHY_REG_1_CLKOBSSEL_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_MSB			24
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_LSB			24
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_MASK			0x01000000
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_DATAOBSEN_MASK) >> PCIE_RC2_PHY_REG_1_DATAOBSEN_LSB)
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_DATAOBSEN_LSB) & PCIE_RC2_PHY_REG_1_DATAOBSEN_MASK)
#define PCIE_RC2_PHY_REG_1_DATAOBSEN_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_MSB			23
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_LSB			23
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_MASK			0x00800000
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_FUNCTESTEN_MASK) >> PCIE_RC2_PHY_REG_1_FUNCTESTEN_LSB)
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_FUNCTESTEN_LSB) & PCIE_RC2_PHY_REG_1_FUNCTESTEN_MASK)
#define PCIE_RC2_PHY_REG_1_FUNCTESTEN_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_MSB			22
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_LSB			22
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_MASK			0x00400000
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_DISABLE_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_DISABLE_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_DISABLE_LSB) & PCIE_RC2_PHY_REG_1_SERDES_DISABLE_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_DISABLE_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_RXCLKINV_MSB				21
#define PCIE_RC2_PHY_REG_1_RXCLKINV_LSB				21
#define PCIE_RC2_PHY_REG_1_RXCLKINV_MASK			0x00200000
#define PCIE_RC2_PHY_REG_1_RXCLKINV_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_RXCLKINV_MASK) >> PCIE_RC2_PHY_REG_1_RXCLKINV_LSB)
#define PCIE_RC2_PHY_REG_1_RXCLKINV_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_RXCLKINV_LSB) & PCIE_RC2_PHY_REG_1_RXCLKINV_MASK)
#define PCIE_RC2_PHY_REG_1_RXCLKINV_RESET			0x1 // 1
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_MSB			20
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_LSB			20
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_MASK		0x00100000
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_MASK) >> PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_LSB)
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_LSB) & PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_MASK)
#define PCIE_RC2_PHY_REG_1_FUNCTESTRXCLKINV_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_MSB			19
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_LSB			19
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_MASK		0x00080000
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_MASK) >> PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_LSB)
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_LSB) & PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_MASK)
#define PCIE_RC2_PHY_REG_1_FUNCTESTTXCLKINV_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_MSB			18
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_LSB			18
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_MASK			0x00040000
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_ENABLECLKREQ_MASK) >> PCIE_RC2_PHY_REG_1_ENABLECLKREQ_LSB)
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_ENABLECLKREQ_LSB) & PCIE_RC2_PHY_REG_1_ENABLECLKREQ_MASK)
#define PCIE_RC2_PHY_REG_1_ENABLECLKREQ_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_MSB			17
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_LSB			17
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_MASK			0x00020000
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_FORCELOOPBACK_MASK) >> PCIE_RC2_PHY_REG_1_FORCELOOPBACK_LSB)
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_FORCELOOPBACK_LSB) & PCIE_RC2_PHY_REG_1_FORCELOOPBACK_MASK)
#define PCIE_RC2_PHY_REG_1_FORCELOOPBACK_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_SEL_CLK_MSB				16
#define PCIE_RC2_PHY_REG_1_SEL_CLK_LSB				15
#define PCIE_RC2_PHY_REG_1_SEL_CLK_MASK				0x00018000
#define PCIE_RC2_PHY_REG_1_SEL_CLK_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_SEL_CLK_MASK) >> PCIE_RC2_PHY_REG_1_SEL_CLK_LSB)
#define PCIE_RC2_PHY_REG_1_SEL_CLK_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_SEL_CLK_LSB) & PCIE_RC2_PHY_REG_1_SEL_CLK_MASK)
#define PCIE_RC2_PHY_REG_1_SEL_CLK_RESET			0x2 // 2
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_MSB			14
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_LSB			14
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_MASK			0x00004000
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_LSB) & PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_RX_EQ_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_MSB			13
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_LSB			13
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_MASK			0x00002000
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_LSB) & PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_EN_LCKDT_RESET		0x1 // 1
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_MSB		12
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB		12
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK		0x00001000
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_LSB) & PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_PLL_DISABLE_L1_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_MSB		11
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_LSB		11
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_MASK		0x00000800
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_LSB) & PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_POWER_SAVE_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_MSB			10
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_LSB			9
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_MASK			0x00000600
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_LSB) & PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_CDR_BW_RESET			0x3 // 3
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_MSB			8
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_LSB			7
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_MASK			0x00000180
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_GET(x)			(((x) & PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_SET(x)			(((x) << PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_LSB) & PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_TH_LOS_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_MSB			6
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_LSB			6
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_MASK			0x00000040
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_LSB) & PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_EN_DEEMP_RESET		0x1 // 1
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_MSB			5
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_LSB			5
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_MASK			0x00000020
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_LSB) & PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_HALFTXDR_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_MSB			4
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_LSB			4
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_MASK			0x00000010
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_GET(x)		(((x) & PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_MASK) >> PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_LSB)
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_SET(x)		(((x) << PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_LSB) & PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_MASK)
#define PCIE_RC2_PHY_REG_1_SERDES_SEL_HSP_RESET			0x1 // 1
#define PCIE_RC2_PHY_REG_1_S_MSB				3
#define PCIE_RC2_PHY_REG_1_S_LSB				0
#define PCIE_RC2_PHY_REG_1_S_MASK				0x0000000f
#define PCIE_RC2_PHY_REG_1_S_GET(x)				(((x) & PCIE_RC2_PHY_REG_1_S_MASK) >> PCIE_RC2_PHY_REG_1_S_LSB)
#define PCIE_RC2_PHY_REG_1_S_SET(x)				(((x) << PCIE_RC2_PHY_REG_1_S_LSB) & PCIE_RC2_PHY_REG_1_S_MASK)
#define PCIE_RC2_PHY_REG_1_S_RESET				0xe // 14
#define PCIE_RC2_PHY_REG_1_ADDRESS				0x18116e00

// 0x18116e04	PCIE_RC2_PHY_REG_2
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_MSB			31
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_LSB			24
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_MASK		0xff000000
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_MASK) >> PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_LSB)
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_LSB) & PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_MASK)
#define PCIE_RC2_PHY_REG_2_PRBS_ERROR_COUNT_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_MSB		23
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB		23
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK		0x00800000
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK) >> PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB)
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_LSB) & PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_MASK)
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXELECIDLE_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_MSB		22
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_LSB		22
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_MASK		0x00400000
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_MASK) >> PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_LSB)
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_LSB) & PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_MASK)
#define PCIE_RC2_PHY_REG_2_SDS_SDM_RXDETECTED_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_MSB			21
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_LSB			21
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_MASK			0x00200000
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_MASK) >> PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_LSB)
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_LSB) & PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_MASK)
#define PCIE_RC2_PHY_REG_2_PRBS_SCRAMBLE_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_2_PRBS_START_MSB			20
#define PCIE_RC2_PHY_REG_2_PRBS_START_LSB			20
#define PCIE_RC2_PHY_REG_2_PRBS_START_MASK			0x00100000
#define PCIE_RC2_PHY_REG_2_PRBS_START_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_PRBS_START_MASK) >> PCIE_RC2_PHY_REG_2_PRBS_START_LSB)
#define PCIE_RC2_PHY_REG_2_PRBS_START_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_PRBS_START_LSB) & PCIE_RC2_PHY_REG_2_PRBS_START_MASK)
#define PCIE_RC2_PHY_REG_2_PRBS_START_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_MSB			19
#define PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_LSB			13
#define PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_MASK			0x000fe000
#define PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_MASK) >> PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_LSB)
#define PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_LSB) & PCIE_RC2_PHY_REG_2_PRBS_TS_NUM_MASK)
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_MSB			12
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_LSB			12
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_MASK			0x00001000
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_MASK) >> PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_LSB)
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_LSB) & PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_MASK)
#define PCIE_RC2_PHY_REG_2_TXDETRXOVRVALUE_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_MSB			11
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_LSB			11
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_MASK			0x00000800
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_TXDETRXOVREN_MASK) >> PCIE_RC2_PHY_REG_2_TXDETRXOVREN_LSB)
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_TXDETRXOVREN_LSB) & PCIE_RC2_PHY_REG_2_TXDETRXOVREN_MASK)
#define PCIE_RC2_PHY_REG_2_TXDETRXOVREN_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_MSB			10
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_LSB			10
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_MASK			0x00000400
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_MASK) >> PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_LSB)
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_LSB) & PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_MASK)
#define PCIE_RC2_PHY_REG_2_DATAOBSPRBSERR_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_MSB			9
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_LSB			6
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_MASK			0x000003c0
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_CDRREADYTIMER_MASK) >> PCIE_RC2_PHY_REG_2_CDRREADYTIMER_LSB)
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_CDRREADYTIMER_LSB) & PCIE_RC2_PHY_REG_2_CDRREADYTIMER_MASK)
#define PCIE_RC2_PHY_REG_2_CDRREADYTIMER_RESET			0x7 // 7
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_MSB		5
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_LSB		1
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_MASK		0x0000003e
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_GET(x)		(((x) & PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_MASK) >> PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_LSB)
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_SET(x)		(((x) << PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_LSB) & PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_MASK)
#define PCIE_RC2_PHY_REG_2_TXDETRXTARGETDELAY_RESET		0xc // 12
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_MSB			0
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_LSB			0
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_MASK			0x00000001
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_GET(x)			(((x) & PCIE_RC2_PHY_REG_2_FORCEDETECT_MASK) >> PCIE_RC2_PHY_REG_2_FORCEDETECT_LSB)
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_SET(x)			(((x) << PCIE_RC2_PHY_REG_2_FORCEDETECT_LSB) & PCIE_RC2_PHY_REG_2_FORCEDETECT_MASK)
#define PCIE_RC2_PHY_REG_2_FORCEDETECT_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_2_ADDRESS				0x18116e04

// 0x18116e08	PCIE_RC2_PHY_REG_3
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_MSB		31
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_LSB		28
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_MASK		0xf0000000
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_GET(x)		(((x) & PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_MASK) >> PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_LSB)
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_SET(x)		(((x) << PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_LSB) & PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_MASK)
#define PCIE_RC2_PHY_REG_3_PRBS_COMMA_STATUS_RESET		0x0 // 0
#define PCIE_RC2_PHY_REG_3_SPARE_MSB				27
#define PCIE_RC2_PHY_REG_3_SPARE_LSB				11
#define PCIE_RC2_PHY_REG_3_SPARE_MASK				0x0ffff800
#define PCIE_RC2_PHY_REG_3_SPARE_GET(x)				(((x) & PCIE_RC2_PHY_REG_3_SPARE_MASK) >> PCIE_RC2_PHY_REG_3_SPARE_LSB)
#define PCIE_RC2_PHY_REG_3_SPARE_SET(x)				(((x) << PCIE_RC2_PHY_REG_3_SPARE_LSB) & PCIE_RC2_PHY_REG_3_SPARE_MASK)
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_MSB			10
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_LSB			10
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_MASK			0x00000400
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_SEL_CLK100_MASK) >> PCIE_RC2_PHY_REG_3_SEL_CLK100_LSB)
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_SEL_CLK100_LSB) & PCIE_RC2_PHY_REG_3_SEL_CLK100_MASK)
#define PCIE_RC2_PHY_REG_3_SEL_CLK100_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_MSB			9
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_LSB			9
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_MASK			0x00000200
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_EN_BEACONGEN_MASK) >> PCIE_RC2_PHY_REG_3_EN_BEACONGEN_LSB)
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_EN_BEACONGEN_LSB) & PCIE_RC2_PHY_REG_3_EN_BEACONGEN_MASK)
#define PCIE_RC2_PHY_REG_3_EN_BEACONGEN_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_MSB			8
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_LSB			8
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_MASK			0x00000100
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_TXELECIDLE_MASK) >> PCIE_RC2_PHY_REG_3_TXELECIDLE_LSB)
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_TXELECIDLE_LSB) & PCIE_RC2_PHY_REG_3_TXELECIDLE_MASK)
#define PCIE_RC2_PHY_REG_3_TXELECIDLE_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_SEL_CLK_MSB				7
#define PCIE_RC2_PHY_REG_3_SEL_CLK_LSB				6
#define PCIE_RC2_PHY_REG_3_SEL_CLK_MASK				0x000000c0
#define PCIE_RC2_PHY_REG_3_SEL_CLK_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_SEL_CLK_MASK) >> PCIE_RC2_PHY_REG_3_SEL_CLK_LSB)
#define PCIE_RC2_PHY_REG_3_SEL_CLK_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_SEL_CLK_LSB) & PCIE_RC2_PHY_REG_3_SEL_CLK_MASK)
#define PCIE_RC2_PHY_REG_3_SEL_CLK_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_MSB			5
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_LSB			5
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_MASK			0x00000020
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_RX_DET_REQ_MASK) >> PCIE_RC2_PHY_REG_3_RX_DET_REQ_LSB)
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_RX_DET_REQ_LSB) & PCIE_RC2_PHY_REG_3_RX_DET_REQ_MASK)
#define PCIE_RC2_PHY_REG_3_RX_DET_REQ_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_MSB			4
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_LSB			4
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_MASK			0x00000010
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_MASK) >> PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_LSB)
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_LSB) & PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_MASK)
#define PCIE_RC2_PHY_REG_3_MODE_OCLK_IN_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_EN_PLL_MSB				3
#define PCIE_RC2_PHY_REG_3_EN_PLL_LSB				3
#define PCIE_RC2_PHY_REG_3_EN_PLL_MASK				0x00000008
#define PCIE_RC2_PHY_REG_3_EN_PLL_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_EN_PLL_MASK) >> PCIE_RC2_PHY_REG_3_EN_PLL_LSB)
#define PCIE_RC2_PHY_REG_3_EN_PLL_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_EN_PLL_LSB) & PCIE_RC2_PHY_REG_3_EN_PLL_MASK)
#define PCIE_RC2_PHY_REG_3_EN_PLL_RESET				0x1 // 1
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_MSB				2
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_LSB				2
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_MASK			0x00000004
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_EN_LCKDT_MASK) >> PCIE_RC2_PHY_REG_3_EN_LCKDT_LSB)
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_EN_LCKDT_LSB) & PCIE_RC2_PHY_REG_3_EN_LCKDT_MASK)
#define PCIE_RC2_PHY_REG_3_EN_LCKDT_RESET			0x1 // 1
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_MSB			1
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_LSB			1
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_MASK			0x00000002
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_GET(x)			(((x) & PCIE_RC2_PHY_REG_3_EN_BUFS_RX_MASK) >> PCIE_RC2_PHY_REG_3_EN_BUFS_RX_LSB)
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_SET(x)			(((x) << PCIE_RC2_PHY_REG_3_EN_BUFS_RX_LSB) & PCIE_RC2_PHY_REG_3_EN_BUFS_RX_MASK)
#define PCIE_RC2_PHY_REG_3_EN_BUFS_RX_RESET			0x0 // 0
#define PCIE_RC2_PHY_REG_3_EN_MSB				0
#define PCIE_RC2_PHY_REG_3_EN_LSB				0
#define PCIE_RC2_PHY_REG_3_EN_MASK				0x00000001
#define PCIE_RC2_PHY_REG_3_EN_GET(x)				(((x) & PCIE_RC2_PHY_REG_3_EN_MASK) >> PCIE_RC2_PHY_REG_3_EN_LSB)
#define PCIE_RC2_PHY_REG_3_EN_SET(x)				(((x) << PCIE_RC2_PHY_REG_3_EN_LSB) & PCIE_RC2_PHY_REG_3_EN_MASK)
#define PCIE_RC2_PHY_REG_3_EN_RESET				0x0 // 0
#define PCIE_RC2_PHY_REG_3_ADDRESS				0x18116e08

// 0x18130000	OTP_MEM_0
#define OTP_MEM_0_OTP_MEM_MSB					31
#define OTP_MEM_0_OTP_MEM_LSB					0
#define OTP_MEM_0_OTP_MEM_MASK					0xffffffff
#define OTP_MEM_0_OTP_MEM_GET(x)				(((x) & OTP_MEM_0_OTP_MEM_MASK) >> OTP_MEM_0_OTP_MEM_LSB)
#define OTP_MEM_0_OTP_MEM_SET(x)				(((x) << OTP_MEM_0_OTP_MEM_LSB) & OTP_MEM_0_OTP_MEM_MASK)
#define OTP_MEM_0_OTP_MEM_RESET					0x0 // 0
#define OTP_MEM_0_ADDRESS					0x18130000

// 0x18131000	OTP_INTF0
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_MSB			31
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_LSB			0
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_MASK			0xffffffff
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_GET(x)			(((x) & OTP_INTF0_EFUSE_WR_ENABLE_REG_V_MASK) >> OTP_INTF0_EFUSE_WR_ENABLE_REG_V_LSB)
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_SET(x)			(((x) << OTP_INTF0_EFUSE_WR_ENABLE_REG_V_LSB) & OTP_INTF0_EFUSE_WR_ENABLE_REG_V_MASK)
#define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_RESET			0x0 // 0
#define OTP_INTF0_ADDRESS					0x18131000

// 0x18131004	OTP_INTF1
#define OTP_INTF1_BITMASK_WR_REG_V_MSB				31
#define OTP_INTF1_BITMASK_WR_REG_V_LSB				0
#define OTP_INTF1_BITMASK_WR_REG_V_MASK				0xffffffff
#define OTP_INTF1_BITMASK_WR_REG_V_GET(x)			(((x) & OTP_INTF1_BITMASK_WR_REG_V_MASK) >> OTP_INTF1_BITMASK_WR_REG_V_LSB)
#define OTP_INTF1_BITMASK_WR_REG_V_SET(x)			(((x) << OTP_INTF1_BITMASK_WR_REG_V_LSB) & OTP_INTF1_BITMASK_WR_REG_V_MASK)
#define OTP_INTF1_BITMASK_WR_REG_V_RESET			0x0 // 0
#define OTP_INTF1_ADDRESS					0x18131004

// 0x18131008	OTP_INTF2
#define OTP_INTF2_PG_STROBE_PW_REG_V_MSB			31
#define OTP_INTF2_PG_STROBE_PW_REG_V_LSB			0
#define OTP_INTF2_PG_STROBE_PW_REG_V_MASK			0xffffffff
#define OTP_INTF2_PG_STROBE_PW_REG_V_GET(x)			(((x) & OTP_INTF2_PG_STROBE_PW_REG_V_MASK) >> OTP_INTF2_PG_STROBE_PW_REG_V_LSB)
#define OTP_INTF2_PG_STROBE_PW_REG_V_SET(x)			(((x) << OTP_INTF2_PG_STROBE_PW_REG_V_LSB) & OTP_INTF2_PG_STROBE_PW_REG_V_MASK)
#define OTP_INTF2_PG_STROBE_PW_REG_V_RESET			0x0 // 0
#define OTP_INTF2_ADDRESS					0x18131008

// 0x1813100c	OTP_INTF3
#define OTP_INTF3_RD_STROBE_PW_REG_V_MSB			31
#define OTP_INTF3_RD_STROBE_PW_REG_V_LSB			0
#define OTP_INTF3_RD_STROBE_PW_REG_V_MASK			0xffffffff
#define OTP_INTF3_RD_STROBE_PW_REG_V_GET(x)			(((x) & OTP_INTF3_RD_STROBE_PW_REG_V_MASK) >> OTP_INTF3_RD_STROBE_PW_REG_V_LSB)
#define OTP_INTF3_RD_STROBE_PW_REG_V_SET(x)			(((x) << OTP_INTF3_RD_STROBE_PW_REG_V_LSB) & OTP_INTF3_RD_STROBE_PW_REG_V_MASK)
#define OTP_INTF3_RD_STROBE_PW_REG_V_RESET			0x0 // 0
#define OTP_INTF3_ADDRESS					0x1813100c

// 0x18131010	OTP_INTF4
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_MSB			31
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_LSB			0
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_MASK			0xffffffff
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_GET(x)			(((x) & OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_MASK) >> OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_LSB)
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_SET(x)			(((x) << OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_LSB) & OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_MASK)
#define OTP_INTF4_VDDQ_SETTLE_TIME_REG_V_RESET			0x0 // 0
#define OTP_INTF4_ADDRESS					0x18131010

// 0x18131014	OTP_INTF5
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_MSB			0
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_LSB			0
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_MASK			0x00000001
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_GET(x)			(((x) & OTP_INTF5_EFUSE_INT_ENABLE_REG_V_MASK) >> OTP_INTF5_EFUSE_INT_ENABLE_REG_V_LSB)
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_SET(x)			(((x) << OTP_INTF5_EFUSE_INT_ENABLE_REG_V_LSB) & OTP_INTF5_EFUSE_INT_ENABLE_REG_V_MASK)
#define OTP_INTF5_EFUSE_INT_ENABLE_REG_V_RESET			0x0 // 0
#define OTP_INTF5_ADDRESS					0x18131014

// 0x18131018	OTP_STATUS0
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_MSB			2
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB			2
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK			0x00000004
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_GET(x)		(((x) & OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK) >> OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB)
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_SET(x)		(((x) << OTP_STATUS0_EFUSE_READ_DATA_VALID_LSB) & OTP_STATUS0_EFUSE_READ_DATA_VALID_MASK)
#define OTP_STATUS0_EFUSE_READ_DATA_VALID_RESET			0x0 // 0
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_MSB			1
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB			1
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK			0x00000002
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_GET(x)			(((x) & OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK) >> OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB)
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_SET(x)			(((x) << OTP_STATUS0_EFUSE_ACCESS_BUSY_LSB) & OTP_STATUS0_EFUSE_ACCESS_BUSY_MASK)
#define OTP_STATUS0_EFUSE_ACCESS_BUSY_RESET			0x0 // 0
#define OTP_STATUS0_OTP_SM_BUSY_MSB				0
#define OTP_STATUS0_OTP_SM_BUSY_LSB				0
#define OTP_STATUS0_OTP_SM_BUSY_MASK				0x00000001
#define OTP_STATUS0_OTP_SM_BUSY_GET(x)				(((x) & OTP_STATUS0_OTP_SM_BUSY_MASK) >> OTP_STATUS0_OTP_SM_BUSY_LSB)
#define OTP_STATUS0_OTP_SM_BUSY_SET(x)				(((x) << OTP_STATUS0_OTP_SM_BUSY_LSB) & OTP_STATUS0_OTP_SM_BUSY_MASK)
#define OTP_STATUS0_OTP_SM_BUSY_RESET				0x0 // 0
#define OTP_STATUS0_ADDRESS					0x18131018

// 0x1813101c	OTP_STATUS1
#define OTP_STATUS1_EFUSE_READ_DATA_MSB				31
#define OTP_STATUS1_EFUSE_READ_DATA_LSB				0
#define OTP_STATUS1_EFUSE_READ_DATA_MASK			0xffffffff
#define OTP_STATUS1_EFUSE_READ_DATA_GET(x)			(((x) & OTP_STATUS1_EFUSE_READ_DATA_MASK) >> OTP_STATUS1_EFUSE_READ_DATA_LSB)
#define OTP_STATUS1_EFUSE_READ_DATA_SET(x)			(((x) << OTP_STATUS1_EFUSE_READ_DATA_LSB) & OTP_STATUS1_EFUSE_READ_DATA_MASK)
#define OTP_STATUS1_EFUSE_READ_DATA_RESET			0x0 // 0
#define OTP_STATUS1_ADDRESS					0x1813101c

// 0x18131020	OTP_INTF6
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_MSB			31
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_LSB			0
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_MASK		0xffffffff
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_GET(x)		(((x) & OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_MASK) >> OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_LSB)
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_SET(x)		(((x) << OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_LSB) & OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_MASK)
#define OTP_INTF6_BACK_TO_BACK_ACCESS_DELAY_RESET		0x0 // 0
#define OTP_INTF6_ADDRESS					0x18131020

// 0x18131024	OTP_LDO_CONTROL
#define OTP_LDO_CONTROL_ENABLE_MSB				0
#define OTP_LDO_CONTROL_ENABLE_LSB				0
#define OTP_LDO_CONTROL_ENABLE_MASK				0x00000001
#define OTP_LDO_CONTROL_ENABLE_GET(x)				(((x) & OTP_LDO_CONTROL_ENABLE_MASK) >> OTP_LDO_CONTROL_ENABLE_LSB)
#define OTP_LDO_CONTROL_ENABLE_SET(x)				(((x) << OTP_LDO_CONTROL_ENABLE_LSB) & OTP_LDO_CONTROL_ENABLE_MASK)
#define OTP_LDO_CONTROL_ENABLE_RESET				0x0 // 0
#define OTP_LDO_CONTROL_ADDRESS					0x18131024

// 0x18131028	OTP_LDO_POWER_GOOD
#define OTP_LDO_POWER_GOOD_DELAY_MSB				11
#define OTP_LDO_POWER_GOOD_DELAY_LSB				0
#define OTP_LDO_POWER_GOOD_DELAY_MASK				0x00000fff
#define OTP_LDO_POWER_GOOD_DELAY_GET(x)				(((x) & OTP_LDO_POWER_GOOD_DELAY_MASK) >> OTP_LDO_POWER_GOOD_DELAY_LSB)
#define OTP_LDO_POWER_GOOD_DELAY_SET(x)				(((x) << OTP_LDO_POWER_GOOD_DELAY_LSB) & OTP_LDO_POWER_GOOD_DELAY_MASK)
#define OTP_LDO_POWER_GOOD_DELAY_RESET				0x0 // 0
#define OTP_LDO_POWER_GOOD_ADDRESS				0x18131028

// 0x1813102c	OTP_LDO_STATUS
#define OTP_LDO_STATUS_POWER_ON_MSB				0
#define OTP_LDO_STATUS_POWER_ON_LSB				0
#define OTP_LDO_STATUS_POWER_ON_MASK				0x00000001
#define OTP_LDO_STATUS_POWER_ON_GET(x)				(((x) & OTP_LDO_STATUS_POWER_ON_MASK) >> OTP_LDO_STATUS_POWER_ON_LSB)
#define OTP_LDO_STATUS_POWER_ON_SET(x)				(((x) << OTP_LDO_STATUS_POWER_ON_LSB) & OTP_LDO_STATUS_POWER_ON_MASK)
#define OTP_LDO_STATUS_POWER_ON_RESET				0x0 // 0
#define OTP_LDO_STATUS_ADDRESS					0x1813102c

// 0x18131030	OTP_VDDQ_HOLD_TIME
#define OTP_VDDQ_HOLD_TIME_DELAY_MSB				31
#define OTP_VDDQ_HOLD_TIME_DELAY_LSB				0
#define OTP_VDDQ_HOLD_TIME_DELAY_MASK				0xffffffff
#define OTP_VDDQ_HOLD_TIME_DELAY_GET(x)				(((x) & OTP_VDDQ_HOLD_TIME_DELAY_MASK) >> OTP_VDDQ_HOLD_TIME_DELAY_LSB)
#define OTP_VDDQ_HOLD_TIME_DELAY_SET(x)				(((x) << OTP_VDDQ_HOLD_TIME_DELAY_LSB) & OTP_VDDQ_HOLD_TIME_DELAY_MASK)
#define OTP_VDDQ_HOLD_TIME_DELAY_RESET				0x0 // 0
#define OTP_VDDQ_HOLD_TIME_ADDRESS				0x18131030

// 0x18131034	OTP_PGENB_SETUP_HOLD_TIME
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_MSB			31
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_LSB			0
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_MASK			0xffffffff
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_GET(x)			(((x) & OTP_PGENB_SETUP_HOLD_TIME_DELAY_MASK) >> OTP_PGENB_SETUP_HOLD_TIME_DELAY_LSB)
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_SET(x)			(((x) << OTP_PGENB_SETUP_HOLD_TIME_DELAY_LSB) & OTP_PGENB_SETUP_HOLD_TIME_DELAY_MASK)
#define OTP_PGENB_SETUP_HOLD_TIME_DELAY_RESET			0x0 // 0
#define OTP_PGENB_SETUP_HOLD_TIME_ADDRESS			0x18131034

// 0x18131038	OTP_STROBE_PULSE_INTERVAL
#define OTP_STROBE_PULSE_INTERVAL_DELAY_MSB			31
#define OTP_STROBE_PULSE_INTERVAL_DELAY_LSB			0
#define OTP_STROBE_PULSE_INTERVAL_DELAY_MASK			0xffffffff
#define OTP_STROBE_PULSE_INTERVAL_DELAY_GET(x)			(((x) & OTP_STROBE_PULSE_INTERVAL_DELAY_MASK) >> OTP_STROBE_PULSE_INTERVAL_DELAY_LSB)
#define OTP_STROBE_PULSE_INTERVAL_DELAY_SET(x)			(((x) << OTP_STROBE_PULSE_INTERVAL_DELAY_LSB) & OTP_STROBE_PULSE_INTERVAL_DELAY_MASK)
#define OTP_STROBE_PULSE_INTERVAL_DELAY_RESET			0x0 // 0
#define OTP_STROBE_PULSE_INTERVAL_ADDRESS			0x18131038

// 0x1813103c	OTP_CSB_ADDR_LOAD_SETUP_HOLD
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_MSB			31
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_LSB			0
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_MASK			0xffffffff
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_GET(x)		(((x) & OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_MASK) >> OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_LSB)
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_SET(x)		(((x) << OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_LSB) & OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_MASK)
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_RESET		0x0 // 0
#define OTP_CSB_ADDR_LOAD_SETUP_HOLD_ADDRESS			0x1813103c

// 0x18230000	PCIE_EP_REG_0
#define PCIE_EP_REG_0_DATA_MSB					31
#define PCIE_EP_REG_0_DATA_LSB					0
#define PCIE_EP_REG_0_DATA_MASK					0xffffffff
#define PCIE_EP_REG_0_DATA_GET(x)				(((x) & PCIE_EP_REG_0_DATA_MASK) >> PCIE_EP_REG_0_DATA_LSB)
#define PCIE_EP_REG_0_DATA_SET(x)				(((x) << PCIE_EP_REG_0_DATA_LSB) & PCIE_EP_REG_0_DATA_MASK)
#define PCIE_EP_REG_0_DATA_RESET				0x0 // 0
#define PCIE_EP_REG_0_ADDRESS					0x18230000

#define ATH_RAM_TYPE()		(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & (RST_BOOTSTRAP_SDRAM_DISABLE_MASK | RST_BOOTSTRAP_DDR_SELECT_MASK))
#define ATH_REF_CLK()		(RST_BOOTSTRAP_REF_CLK_GET(ath_reg_rd(RST_BOOTSTRAP_ADDRESS)) ? 40 : 25)

#define CPU_DDR_CLOCK_CONTROL_PLL_BYPASS_MASK		\
	~(CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_MASK)

#define CPU_DDR_CLOCK_CONTROL_POST_DIV_MASK		\
	~(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_MASK |	\
	  CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_MASK |	\
	  CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_MASK)

#define	DDR_PLL_40_INIT_VAL		(DDR_PLL_CONFIG_PLLPWD_SET(0) |	\
					 DDR_PLL_CONFIG_REFDIV_SET(1) |	\
					 DDR_PLL_CONFIG_NINT_SET(10) |	\
					 DDR_PLL_CONFIG_OUTDIV_SET(1) |	\
					 DDR_PLL_CONFIG_NFRAC_SET(0))

#define	DDR_PLL_25_INIT_VAL		(DDR_PLL_CONFIG_PLLPWD_SET(0) |	\
					 DDR_PLL_CONFIG_REFDIV_SET(1) |	\
					 DDR_PLL_CONFIG_NINT_SET(16) |	\
					 DDR_PLL_CONFIG_OUTDIV_SET(1) |	\
					 DDR_PLL_CONFIG_NFRAC_SET(0))

#define	CPU_DDR_CLOCK_CONTROL_INIT_MASK			\
	(CPU_DDR_CLOCK_CONTROL_PLL_BYPASS_MASK &	\
	 CPU_DDR_CLOCK_CONTROL_POST_DIV_MASK)

#define CPU_DDR_CLOCK_CONTROL_INIT_VAL			\
	(CPU_DDR_CLOCK_CONTROL_AHB_POST_DIV_SET(3) |	\
	 CPU_DDR_CLOCK_CONTROL_DDR_POST_DIV_SET(1) |	\
	 CPU_DDR_CLOCK_CONTROL_CPU_POST_DIV_SET(1))

#define SWITCH_CLOCK_SPARE_INIT_MASK			\
	~(SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)

#define SWITCH_CLOCK_SPARE_40_INIT_VAL			\
	 SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(5)

#define SWITCH_CLOCK_SPARE_25_INIT_VAL			\
	 SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SET(2)

#define SWITCH_CLOCK_SPARE_INIT_MASK			\
	~(SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK)

#define DDR_PLL_INIT_MASK		~(DDR_PLL_CONFIG_PLLPWD_MASK |	\
					  DDR_PLL_CONFIG_REFDIV_MASK |	\
					  DDR_PLL_CONFIG_NINT_MASK |	\
					  DDR_PLL_CONFIG_OUTDIV_MASK |	\
					  DDR_PLL_CONFIG_NFRAC_MASK)

#define ATH_GET_REF_FREQ(a)	\
	((((a) & RST_BOOTSTRAP_REF_CLK_MASK) ? 40 : 25) * 1000 * 1000)

#define ATH_GE0_BASE			0x19000000
#define ATH_GE1_BASE			0x1a000000

#define ATH_SRAM_BASE			0xbd000000

// 32KB, reserve 16 bytes for WARM_START indicator
#define ATH_SRAM_SIZE			0x7FF0
#define ATH_STACK_SIZE			0x400
#define ATH_INIT_SP_OFFSET		ATH_SRAM_SIZE

#define ATH_DCACHE_SIZE			32768
#define ATH_ICACHE_SIZE			65536
#define ATH_CACHELINE_SIZE		32

#define ATH_BAUD_RATE			115200

#define ATH_NAND_FLASH_BASE		0x1b800000u

#define ATH_USB_ID_PRODUCT		0x9440

#define ATH_PCI_DID_VID			0x0039168c

#define ATH_MDC_GPIO_PIN		11
#define ATH_MDIO_GPIO_PIN		18
#define ATH_GPIO_OUT_FUNC_ADDR		GPIO_OUT_FUNCTION4_ADDRESS
#define ATH_GPIO_OUT_FUNC_EN_MASK	GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_MASK
#define ATH_GPIO_OUT_FUNC_EN_SET	GPIO_OUT_FUNCTION4_ENABLE_GPIO_18_SET
#define ATH_MII_EXT_MDI			1
#define ATH_MDIO_PHY_ADDR		0x7

#endif /* _944x_H_ */
